From c484da1a98610d783131a3a3998c0a999b97f9f5 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 9 Nov 2019 14:29:04 +0100 Subject: sb/intel/i82801jx: Add common code for LPC decode Change-Id: Id706da33f06ceeec39ea50301130770226f0474e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36701 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/mainboard/asus/p5ql-em/romstage.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) (limited to 'src/mainboard/asus/p5ql-em/romstage.c') diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c index 614f4874e1..142ee73e49 100644 --- a/src/mainboard/asus/p5ql-em/romstage.c +++ b/src/mainboard/asus/p5ql-em/romstage.c @@ -117,16 +117,6 @@ static void mb_gpio_init(void) RCBA8(0x31ff); } -static void ich10_enable_lpc(void) -{ - /* Configure serial IRQs.*/ - pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); - pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF1_LPC_EN | KBC_LPC_EN - | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); - /* Hardware monitor IO range */ - pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295); -} - void mainboard_romstage_entry(void) { /* This board has first dimm slot of each channel hooked up to @@ -138,7 +128,7 @@ void mainboard_romstage_entry(void) u8 s3_resume; /* Set southbridge and Super I/O GPIOs. */ - ich10_enable_lpc(); + i82801jx_lpc_setup(); mb_gpio_init(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -- cgit v1.2.3