From fa5d0f835b1f3bb8907e616913cbf7b91d09ef26 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 19:11:50 +0100 Subject: nb/intel/sandybridge: Set up console in bootblock Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/asus/p8h61-m_pro/romstage.c | 78 ------------------------------- 1 file changed, 78 deletions(-) delete mode 100644 src/mainboard/asus/p8h61-m_pro/romstage.c (limited to 'src/mainboard/asus/p8h61-m_pro/romstage.c') diff --git a/src/mainboard/asus/p8h61-m_pro/romstage.c b/src/mainboard/asus/p8h61-m_pro/romstage.c deleted file mode 100644 index ff5a67748d..0000000000 --- a/src/mainboard/asus/p8h61-m_pro/romstage.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Angel Pons - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -#define GLOBAL_DEV PNP_DEV(0x2e, 0) -#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) -#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) - -void mainboard_pch_lpc_setup(void) -{ - /* Enable the Super IO */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | - KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); -} - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - -void mainboard_config_superio(void) -{ - /* Enable UART */ - nuvoton_pnp_enter_conf_state(GLOBAL_DEV); - - /* Select SIO pin states. */ - pnp_write_config(GLOBAL_DEV, 0x1c, 0x83); - pnp_write_config(GLOBAL_DEV, 0x24, 0x30); - pnp_write_config(GLOBAL_DEV, 0x27, 0x40); - pnp_write_config(GLOBAL_DEV, 0x2a, 0x20); - - /* Power RAM in S3. */ - pnp_set_logical_device(ACPI_DEV); - pnp_write_config(ACPI_DEV, 0xe4, 0x10); - - pnp_set_logical_device(SERIAL_DEV); - - nuvoton_pnp_exit_conf_state(GLOBAL_DEV); - - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} -- cgit v1.2.3