From dad7f37f729cee52c8839e18803042e5cf2309c7 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 1 Jan 2020 19:04:55 +0100 Subject: mb/asus/p8h61-m_pro/devicetree.cb: Drop zero fields They default to zero already. Change-Id: I5c99043f16bc65de952afa0ce8d40bf947bfee15 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/38065 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/asus/p8h61-m_pro/devicetree.cb | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mainboard/asus/p8h61-m_pro') diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index e791d70976..166a625a82 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -32,9 +32,7 @@ chip northbridge/intel/sandybridge device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" - register "docking_supported" = "0" register "gen1_dec" = "0x000c0291" # HWM - register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" -- cgit v1.2.3