From bf53acca5e9c6b61086e42eb9e73fd4bb59a6f31 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 21:14:39 +0100 Subject: nb/intel/x4x: Move boilerplate romstage to a common location This adds 3 mb romstage callbacks: - void mb_lpc_setup(void) to be used to set up the superio - void mb_get_spd_map(u8 spd_map[4]) to get I2C addresses of SPDs - (optional)mb_pre_raminit_setup(int s3_resume) to set up mainboard specific things before the raminit. Change-Id: Ic3b838856b3076ed05eeeea7c0656c2078462272 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36758 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/asus/p5qc/romstage.c | 46 ++++++------------------------ src/mainboard/asus/p5ql-em/romstage.c | 51 ++++++++++------------------------ src/mainboard/asus/p5qpl-am/romstage.c | 48 ++++++++------------------------ 3 files changed, 35 insertions(+), 110 deletions(-) (limited to 'src/mainboard/asus') diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index 9a90f74189..53aa176b38 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -14,57 +14,27 @@ * GNU General Public License for more details. */ -#include -#include #include -#include #include -#include #include #include #define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) -/* Early mainboard specific GPIO setup. - * We should use standard gpio.h eventually - */ - -static void mb_misc_rcba(void) +void mb_lpc_setup(void) { /* TODO? */ RCBA32(RCBA_CG) = 0xbf7f001f; RCBA32(0x3430) = 0x00000002; RCBA32(0x3f00) = 0x00000038; -} -void mainboard_romstage_entry(void) -{ - const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801jx_lpc_setup(); - mb_misc_rcba(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} - console_init(); - - enable_smbus(); - - i82801jx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[1] = 0x51; + spd_map[2] = 0x52; + spd_map[3] = 0x53; } diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c index c7ade1c541..fa22a645d4 100644 --- a/src/mainboard/asus/p5ql-em/romstage.c +++ b/src/mainboard/asus/p5ql-em/romstage.c @@ -12,22 +12,22 @@ * GNU General Public License for more details. */ -#include #include #include -#include -#include #include #include #include -#include #include #include #include #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +void mb_lpc_setup(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} static u8 msr_get_fsb(void) { @@ -103,41 +103,20 @@ static int setup_sio_gpio(void) return need_reset; } -void mainboard_romstage_entry(void) +void mb_pre_raminit_setup(int s3_resume) { - /* This board has first dimm slot of each channel hooked up to - rank0 and rank1, while the second dimm slot is only connected - to rank1. The raminit does not support such setups - const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; */ - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801jx_lpc_setup(); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - enable_smbus(); - - i82801jx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - if (!s3_resume && setup_sio_gpio()) { printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); full_reset(); } +} - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); +void mb_get_spd_map(u8 spd_map[4]) +{ + /* This board has first dimm slot of each channel hooked up to + rank0 and rank1, while the second dimm slot is only connected + to rank1. The raminit does not support such setups. So only the + first dimms of each channel are used. */ + spd_map[0] = 0x50; + spd_map[2] = 0x52; } diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index de3972db4e..ad16c0f72a 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -17,20 +17,20 @@ #include #include -#include #include -#include #include #include #include -#include -#include #include #include #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +void mb_lpc_setup(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} static u8 msr_get_fsb(void) { @@ -127,40 +127,16 @@ static int setup_sio_gpio(void) return need_reset; } -void mainboard_romstage_entry(void) +void mb_pre_raminit_setup(int s3_resume) { - // ch0 ch1 - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801gx_lpc_setup(); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - enable_smbus(); - - i82801gx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - if (!s3_resume && setup_sio_gpio()) { - printk(BIOS_DEBUG, - "Needs reset to configure CPU BSEL straps\n"); + printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); full_reset(); } +} - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); - +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x52; } -- cgit v1.2.3