From e94cda578c6a91538c05cc8590752435136268b4 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 17 May 2021 12:31:29 +0200 Subject: mb/asus/p8h61-m_lx3_r2_0: Transform into variant setup Get ready to squash all Asus H61 boards together, so as to factor out lots of redundant code. Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX3 R2.0 remains identical when not adding the .config file in it. Change-Id: I738197bf4d5ea8b879ae26ecbcb0cf3714316662 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/54372 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/asus/h61-series/Kconfig | 32 ++++ src/mainboard/asus/h61-series/Kconfig.name | 8 + src/mainboard/asus/h61-series/Makefile.inc | 8 + src/mainboard/asus/h61-series/acpi/ec.asl | 0 src/mainboard/asus/h61-series/acpi/platform.asl | 10 + src/mainboard/asus/h61-series/acpi/superio.asl | 3 + src/mainboard/asus/h61-series/board_info.txt | 5 + src/mainboard/asus/h61-series/dsdt.asl | 26 +++ src/mainboard/asus/h61-series/hda_verb.c | 0 .../variants/p8h61-m_lx3_r2_0/board_info.txt | 7 + .../h61-series/variants/p8h61-m_lx3_r2_0/data.vbt | Bin 0 -> 7168 bytes .../variants/p8h61-m_lx3_r2_0/devicetree.cb | 85 +++++++++ .../variants/p8h61-m_lx3_r2_0/early_init.c | 55 ++++++ .../variants/p8h61-m_lx3_r2_0/gma-mainboard.ads | 13 ++ .../h61-series/variants/p8h61-m_lx3_r2_0/gpio.c | 212 +++++++++++++++++++++ .../variants/p8h61-m_lx3_r2_0/hda_verb.c | 25 +++ src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig | 29 --- src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name | 2 - src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc | 7 - src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl | 0 .../asus/p8h61-m_lx3_r2_0/acpi/platform.asl | 10 - .../asus/p8h61-m_lx3_r2_0/acpi/superio.asl | 3 - src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt | 7 - src/mainboard/asus/p8h61-m_lx3_r2_0/data.vbt | Bin 7168 -> 0 bytes src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb | 85 --------- src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl | 26 --- src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c | 55 ------ .../asus/p8h61-m_lx3_r2_0/gma-mainboard.ads | 13 -- src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c | 212 --------------------- src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c | 25 --- 30 files changed, 489 insertions(+), 474 deletions(-) create mode 100644 src/mainboard/asus/h61-series/Kconfig create mode 100644 src/mainboard/asus/h61-series/Kconfig.name create mode 100644 src/mainboard/asus/h61-series/Makefile.inc create mode 100644 src/mainboard/asus/h61-series/acpi/ec.asl create mode 100644 src/mainboard/asus/h61-series/acpi/platform.asl create mode 100644 src/mainboard/asus/h61-series/acpi/superio.asl create mode 100644 src/mainboard/asus/h61-series/board_info.txt create mode 100644 src/mainboard/asus/h61-series/dsdt.asl create mode 100644 src/mainboard/asus/h61-series/hda_verb.c create mode 100644 src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/board_info.txt create mode 100644 src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/data.vbt create mode 100644 src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb create mode 100644 src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c create mode 100644 src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/gma-mainboard.ads create mode 100644 src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/gpio.c create mode 100644 src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/hda_verb.c delete mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig delete mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name delete mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc delete mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl delete mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl delete mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl delete mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt delete mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/data.vbt delete mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb delete mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl delete mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c delete mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads delete mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c delete mode 100644 src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c (limited to 'src/mainboard/asus') diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig new file mode 100644 index 0000000000..2ef6642788 --- /dev/null +++ b/src/mainboard/asus/h61-series/Kconfig @@ -0,0 +1,32 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASUS_H61_SERIES + bool + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + +if BOARD_ASUS_H61_SERIES + +config MAINBOARD_DIR + string + default "asus/h61-series" + +config VARIANT_DIR + string + default "p8h61-m_lx3_r2_0" if BOARD_ASUS_P8H61_M_LX3_R2_0 + +config MAINBOARD_PART_NUMBER + string + default "P8H61-M LX3 R2.0" if BOARD_ASUS_P8H61_M_LX3_R2_0 + +config DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" + +endif diff --git a/src/mainboard/asus/h61-series/Kconfig.name b/src/mainboard/asus/h61-series/Kconfig.name new file mode 100644 index 0000000000..14ca540753 --- /dev/null +++ b/src/mainboard/asus/h61-series/Kconfig.name @@ -0,0 +1,8 @@ +config BOARD_ASUS_P8H61_M_LX3_R2_0 + bool "P8H61-M LX3 R2.0" + select BOARD_ASUS_H61_SERIES + select BOARD_ROMSIZE_KB_8192 + select NO_UART_ON_SUPERIO + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + select SUPERIO_NUVOTON_NCT6779D diff --git a/src/mainboard/asus/h61-series/Makefile.inc b/src/mainboard/asus/h61-series/Makefile.inc new file mode 100644 index 0000000000..e339285620 --- /dev/null +++ b/src/mainboard/asus/h61-series/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += variants/$(VARIANT_DIR)/early_init.c +romstage-y += variants/$(VARIANT_DIR)/early_init.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/asus/h61-series/acpi/ec.asl b/src/mainboard/asus/h61-series/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/asus/h61-series/acpi/platform.asl b/src/mainboard/asus/h61-series/acpi/platform.asl new file mode 100644 index 0000000000..7da03bfddd --- /dev/null +++ b/src/mainboard/asus/h61-series/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_PTS, 1) +{ +} + +Method(_WAK, 1) +{ + Return(Package(){0, 0}) +} diff --git a/src/mainboard/asus/h61-series/acpi/superio.asl b/src/mainboard/asus/h61-series/acpi/superio.asl new file mode 100644 index 0000000000..ee2eabeb75 --- /dev/null +++ b/src/mainboard/asus/h61-series/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/asus/h61-series/board_info.txt b/src/mainboard/asus/h61-series/board_info.txt new file mode 100644 index 0000000000..8f74c04efd --- /dev/null +++ b/src/mainboard/asus/h61-series/board_info.txt @@ -0,0 +1,5 @@ +Category: desktop +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/h61-series/dsdt.asl b/src/mainboard/asus/h61-series/dsdt.asl new file mode 100644 index 0000000000..e8e2b3a3e5 --- /dev/null +++ b/src/mainboard/asus/h61-series/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include + #include "acpi/platform.asl" + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asus/h61-series/hda_verb.c b/src/mainboard/asus/h61-series/hda_verb.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/board_info.txt b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/board_info.txt new file mode 100644 index 0000000000..3e3c173aa9 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/us/Motherboards/P8H61M_LX3_R20 +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/data.vbt b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/data.vbt new file mode 100644 index 0000000000..e5be40c56b Binary files /dev/null and b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/data.vbt differ diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb new file mode 100644 index 0000000000..317f9cc22b --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb @@ -0,0 +1,85 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0 on + subsystemid 0x1043 0x844d inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x000c0291" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 off end # Intel GbE + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio + + device pci 1c.0 on end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 off end # RP #3 + device pci 1c.3 on end # RP #4: PCIEX1_1 + device pci 1c.4 on end # RP #5: PCIEX1_2 + device pci 1c.5 on end # RP #6: RTL8111 GbE NIC + + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-8 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 + device pnp 2e.108 on end # GPIO0 + device pnp 2e.9 off end # GPIO1-8 + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 on end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # H/W Monitor, FP LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # Push-pull/Open-drain + device pnp 2e.14 off end # PORT80 UART + device pnp 2e.16 off end # Deep Sleep + end + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c new file mode 100644 index 0000000000..33efaf6e04 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x00); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x71); + pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e); + pnp_write_config(GLOBAL_DEV, 0x22, 0xd7); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x48); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Do not enable UART, the header is not populated by default */ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/gma-mainboard.ads b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/gma-mainboard.ads new file mode 100644 index 0000000000..53464cafb4 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/gma-mainboard.ads @@ -0,0 +1,13 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := (Analog, others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/gpio.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/gpio.c new file mode 100644 index 0000000000..4c326c4272 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/gpio.c @@ -0,0 +1,212 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio63 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio57 = GPIO_RESET_RSMRST, + .gpio63 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/hda_verb.c new file mode 100644 index 0000000000..7988e2b4ad --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x11060397, /* Codec Vendor / Device ID: VIA VT1708S */ + 0x10438415, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10438415), + AZALIA_PIN_CFG(0, 0x19, 0x410110f0), + AZALIA_PIN_CFG(0, 0x1a, 0x01a19036), + AZALIA_PIN_CFG(0, 0x1b, 0x0181303e), + AZALIA_PIN_CFG(0, 0x1c, 0x01014010), + AZALIA_PIN_CFG(0, 0x1d, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1e, 0x02a19037), + AZALIA_PIN_CFG(0, 0x1f, 0x503701f0), + AZALIA_PIN_CFG(0, 0x20, 0x585600f0), + AZALIA_PIN_CFG(0, 0x21, 0x474411f0), + AZALIA_PIN_CFG(0, 0x22, 0x410160f0), + AZALIA_PIN_CFG(0, 0x23, 0x410120f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig deleted file mode 100644 index 16fbbb8af7..0000000000 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -if BOARD_ASUS_P8H61_M_LX3_R2_0 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select INTEL_GMA_HAVE_VBT - select MAINBOARD_HAS_LIBGFXINIT - select NO_UART_ON_SUPERIO - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select REALTEK_8168_RESET - select RT8168_SET_LED_MODE - select SERIRQ_CONTINUOUS_MODE - select SOUTHBRIDGE_INTEL_BD82X6X - select SUPERIO_NUVOTON_NCT6779D - select USE_NATIVE_RAMINIT - -config MAINBOARD_DIR - string - default "asus/p8h61-m_lx3_r2_0" - -config MAINBOARD_PART_NUMBER - string - default "P8H61-M LX3 R2.0" - -endif diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name deleted file mode 100644 index 6d10dcfc39..0000000000 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_P8H61_M_LX3_R2_0 - bool "P8H61-M LX3 R2.0" diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc b/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc deleted file mode 100644 index 7167e10123..0000000000 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -bootblock-y += early_init.c -bootblock-y += gpio.c - -romstage-y += early_init.c -romstage-y += gpio.c - -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl deleted file mode 100644 index 7da03bfddd..0000000000 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Method(_PTS, 1) -{ -} - -Method(_WAK, 1) -{ - Return(Package(){0, 0}) -} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl deleted file mode 100644 index ee2eabeb75..0000000000 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt b/src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt deleted file mode 100644 index 3e3c173aa9..0000000000 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: https://www.asus.com/us/Motherboards/P8H61M_LX3_R20 -ROM package: DIP-8 -ROM protocol: SPI -ROM socketed: y -Flashrom support: y -Release year: 2012 diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/data.vbt b/src/mainboard/asus/p8h61-m_lx3_r2_0/data.vbt deleted file mode 100644 index e5be40c56b..0000000000 Binary files a/src/mainboard/asus/p8h61-m_lx3_r2_0/data.vbt and /dev/null differ diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb b/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb deleted file mode 100644 index 317f9cc22b..0000000000 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb +++ /dev/null @@ -1,85 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end - device domain 0 on - subsystemid 0x1043 0x844d inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PEG - device pci 02.0 on end # iGPU - - chip southbridge/intel/bd82x6x - register "c2_latency" = "0x0065" - register "gen1_dec" = "0x000c0291" - register "sata_port_map" = "0x3f" - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - - device pci 16.0 on end # MEI #1 - device pci 16.1 off end # MEI #2 - device pci 16.2 off end # ME IDE-R - device pci 16.3 off end # ME KT - device pci 19.0 off end # Intel GbE - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # HD Audio - - device pci 1c.0 on end # RP #1 - device pci 1c.1 off end # RP #2 - device pci 1c.2 off end # RP #3 - device pci 1c.3 on end # RP #4: PCIEX1_1 - device pci 1c.4 on end # RP #5: PCIEX1_2 - device pci 1c.5 on end # RP #6: RTL8111 GbE NIC - - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge - chip superio/nuvoton/nct6779d - device pnp 2e.1 off end # Parallel - device pnp 2e.2 off end # UART A - device pnp 2e.3 off end # UART B, IR - device pnp 2e.5 on # Keyboard - io 0x60 = 0x0060 - io 0x62 = 0x0064 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GPIO6-8 - device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 - device pnp 2e.108 on end # GPIO0 - device pnp 2e.9 off end # GPIO1-8 - device pnp 2e.109 off end # GPIO1 - device pnp 2e.209 off end # GPIO2 - device pnp 2e.309 off end # GPIO3 - device pnp 2e.409 off end # GPIO4 - device pnp 2e.509 on end # GPIO5 - device pnp 2e.609 off end # GPIO6 - device pnp 2e.709 off end # GPIO7 - device pnp 2e.a on end # ACPI - device pnp 2e.b on # H/W Monitor, FP LED - io 0x60 = 0x0290 - io 0x62 = 0 - irq 0x70 = 0 - end - device pnp 2e.d off end # WDT1 - device pnp 2e.e off end # CIR WAKE-UP - device pnp 2e.f off end # Push-pull/Open-drain - device pnp 2e.14 off end # PORT80 UART - device pnp 2e.16 off end # Deep Sleep - end - end - device pci 1f.2 on end # SATA (AHCI) - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA (Legacy) - device pci 1f.6 off end # Thermal - end - end -end diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl deleted file mode 100644 index e8e2b3a3e5..0000000000 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -DefinitionBlock( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20141018 /* OEM revision */ -) -{ - #include - #include "acpi/platform.asl" - #include - #include - #include - #include - - Device (\_SB.PCI0) - { - #include - #include - } -} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c deleted file mode 100644 index 33efaf6e04..0000000000 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -#define GLOBAL_DEV PNP_DEV(0x2e, 0) -#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - -void bootblock_mainboard_early_init(void) -{ - nuvoton_pnp_enter_conf_state(GLOBAL_DEV); - - /* Select SIO pin states */ - pnp_write_config(GLOBAL_DEV, 0x1a, 0x00); - pnp_write_config(GLOBAL_DEV, 0x1c, 0x71); - pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e); - pnp_write_config(GLOBAL_DEV, 0x22, 0xd7); - pnp_write_config(GLOBAL_DEV, 0x2a, 0x48); - pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); - - /* Power RAM in S3 */ - pnp_set_logical_device(ACPI_DEV); - pnp_write_config(ACPI_DEV, 0xe4, 0x10); - - nuvoton_pnp_exit_conf_state(GLOBAL_DEV); - - /* Do not enable UART, the header is not populated by default */ -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads b/src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads deleted file mode 100644 index 53464cafb4..0000000000 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads +++ /dev/null @@ -1,13 +0,0 @@ --- SPDX-License-Identifier: GPL-2.0-or-later - -with HW.GFX.GMA; -with HW.GFX.GMA.Display_Probing; - -use HW.GFX.GMA; -use HW.GFX.GMA.Display_Probing; - -private package GMA.Mainboard is - - ports : constant Port_List := (Analog, others => Disabled); - -end GMA.Mainboard; diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c deleted file mode 100644 index 4c326c4272..0000000000 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c +++ /dev/null @@ -1,212 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -static const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, - .gpio1 = GPIO_MODE_GPIO, - .gpio2 = GPIO_MODE_GPIO, - .gpio3 = GPIO_MODE_GPIO, - .gpio4 = GPIO_MODE_GPIO, - .gpio5 = GPIO_MODE_GPIO, - .gpio6 = GPIO_MODE_GPIO, - .gpio7 = GPIO_MODE_GPIO, - .gpio8 = GPIO_MODE_GPIO, - .gpio9 = GPIO_MODE_NATIVE, - .gpio10 = GPIO_MODE_GPIO, - .gpio11 = GPIO_MODE_GPIO, - .gpio12 = GPIO_MODE_GPIO, - .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_GPIO, - .gpio15 = GPIO_MODE_GPIO, - .gpio16 = GPIO_MODE_GPIO, - .gpio17 = GPIO_MODE_GPIO, - .gpio18 = GPIO_MODE_NATIVE, - .gpio19 = GPIO_MODE_GPIO, - .gpio20 = GPIO_MODE_GPIO, - .gpio21 = GPIO_MODE_GPIO, - .gpio22 = GPIO_MODE_GPIO, - .gpio23 = GPIO_MODE_GPIO, - .gpio24 = GPIO_MODE_GPIO, - .gpio25 = GPIO_MODE_NATIVE, - .gpio26 = GPIO_MODE_NATIVE, - .gpio27 = GPIO_MODE_GPIO, - .gpio28 = GPIO_MODE_GPIO, - .gpio29 = GPIO_MODE_GPIO, - .gpio30 = GPIO_MODE_NATIVE, - .gpio31 = GPIO_MODE_GPIO, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_OUTPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_INPUT, - .gpio19 = GPIO_DIR_INPUT, - .gpio20 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio22 = GPIO_DIR_INPUT, - .gpio23 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_OUTPUT, - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_INPUT, - .gpio29 = GPIO_DIR_INPUT, - .gpio31 = GPIO_DIR_INPUT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, - .gpio24 = GPIO_LEVEL_LOW, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_reset = { - .gpio24 = GPIO_RESET_RSMRST, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio13 = GPIO_INVERT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_blink = { -}; - -static const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_GPIO, - .gpio33 = GPIO_MODE_GPIO, - .gpio34 = GPIO_MODE_GPIO, - .gpio35 = GPIO_MODE_GPIO, - .gpio36 = GPIO_MODE_GPIO, - .gpio37 = GPIO_MODE_GPIO, - .gpio38 = GPIO_MODE_GPIO, - .gpio39 = GPIO_MODE_GPIO, - .gpio40 = GPIO_MODE_NATIVE, - .gpio41 = GPIO_MODE_NATIVE, - .gpio42 = GPIO_MODE_GPIO, - .gpio43 = GPIO_MODE_NATIVE, - .gpio44 = GPIO_MODE_GPIO, - .gpio45 = GPIO_MODE_GPIO, - .gpio46 = GPIO_MODE_NATIVE, - .gpio47 = GPIO_MODE_NATIVE, - .gpio48 = GPIO_MODE_GPIO, - .gpio49 = GPIO_MODE_GPIO, - .gpio50 = GPIO_MODE_GPIO, - .gpio51 = GPIO_MODE_GPIO, - .gpio52 = GPIO_MODE_GPIO, - .gpio53 = GPIO_MODE_GPIO, - .gpio54 = GPIO_MODE_GPIO, - .gpio55 = GPIO_MODE_GPIO, - .gpio56 = GPIO_MODE_NATIVE, - .gpio57 = GPIO_MODE_GPIO, - .gpio58 = GPIO_MODE_GPIO, - .gpio59 = GPIO_MODE_NATIVE, - .gpio60 = GPIO_MODE_GPIO, - .gpio61 = GPIO_MODE_GPIO, - .gpio62 = GPIO_MODE_NATIVE, - .gpio63 = GPIO_MODE_GPIO, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_INPUT, - .gpio33 = GPIO_DIR_INPUT, - .gpio34 = GPIO_DIR_INPUT, - .gpio35 = GPIO_DIR_INPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_INPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio42 = GPIO_DIR_INPUT, - .gpio44 = GPIO_DIR_INPUT, - .gpio45 = GPIO_DIR_INPUT, - .gpio48 = GPIO_DIR_INPUT, - .gpio49 = GPIO_DIR_INPUT, - .gpio50 = GPIO_DIR_INPUT, - .gpio51 = GPIO_DIR_INPUT, - .gpio52 = GPIO_DIR_INPUT, - .gpio53 = GPIO_DIR_INPUT, - .gpio54 = GPIO_DIR_INPUT, - .gpio55 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_INPUT, - .gpio58 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_INPUT, - .gpio61 = GPIO_DIR_INPUT, - .gpio63 = GPIO_DIR_OUTPUT, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio63 = GPIO_LEVEL_HIGH, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_reset = { - .gpio57 = GPIO_RESET_RSMRST, - .gpio63 = GPIO_RESET_RSMRST, -}; - -static const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_GPIO, - .gpio65 = GPIO_MODE_GPIO, - .gpio66 = GPIO_MODE_GPIO, - .gpio67 = GPIO_MODE_NATIVE, - .gpio68 = GPIO_MODE_GPIO, - .gpio69 = GPIO_MODE_GPIO, - .gpio70 = GPIO_MODE_GPIO, - .gpio71 = GPIO_MODE_GPIO, - .gpio72 = GPIO_MODE_GPIO, - .gpio73 = GPIO_MODE_NATIVE, - .gpio74 = GPIO_MODE_GPIO, - .gpio75 = GPIO_MODE_GPIO, -}; - -static const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_INPUT, - .gpio65 = GPIO_DIR_INPUT, - .gpio66 = GPIO_DIR_INPUT, - .gpio68 = GPIO_DIR_INPUT, - .gpio69 = GPIO_DIR_INPUT, - .gpio70 = GPIO_DIR_INPUT, - .gpio71 = GPIO_DIR_INPUT, - .gpio72 = GPIO_DIR_INPUT, - .gpio74 = GPIO_DIR_INPUT, - .gpio75 = GPIO_DIR_INPUT, -}; - -static const struct pch_gpio_set3 pch_gpio_set3_level = { -}; - -static const struct pch_gpio_set3 pch_gpio_set3_reset = { -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .blink = &pch_gpio_set1_blink, - .invert = &pch_gpio_set1_invert, - .reset = &pch_gpio_set1_reset, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - .reset = &pch_gpio_set2_reset, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - .reset = &pch_gpio_set3_reset, - }, -}; diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c deleted file mode 100644 index 7988e2b4ad..0000000000 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -const u32 cim_verb_data[] = { - 0x11060397, /* Codec Vendor / Device ID: VIA VT1708S */ - 0x10438415, /* Subsystem ID */ - 12, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(0, 0x10438415), - AZALIA_PIN_CFG(0, 0x19, 0x410110f0), - AZALIA_PIN_CFG(0, 0x1a, 0x01a19036), - AZALIA_PIN_CFG(0, 0x1b, 0x0181303e), - AZALIA_PIN_CFG(0, 0x1c, 0x01014010), - AZALIA_PIN_CFG(0, 0x1d, 0x0221401f), - AZALIA_PIN_CFG(0, 0x1e, 0x02a19037), - AZALIA_PIN_CFG(0, 0x1f, 0x503701f0), - AZALIA_PIN_CFG(0, 0x20, 0x585600f0), - AZALIA_PIN_CFG(0, 0x21, 0x474411f0), - AZALIA_PIN_CFG(0, 0x22, 0x410160f0), - AZALIA_PIN_CFG(0, 0x23, 0x410120f0), -}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; -- cgit v1.2.3