From bb45f38eb9d0ecc6f4a1d0ca37c8c52212360c56 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 15:45:05 +0000 Subject: mb/bap/ode_e20XX: Switch away from ROMCC_BOOTBLOCK Warning: not tested on hardware. Signed-off-by: Mike Banon Change-Id: I37a1a95bdf07d99916247095a5bc3ac5349cd98f Reviewed-on: https://review.coreboot.org/c/coreboot/+/38869 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/bap/ode_e20XX/bootblock.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 src/mainboard/bap/ode_e20XX/bootblock.c (limited to 'src/mainboard/bap/ode_e20XX/bootblock.c') diff --git a/src/mainboard/bap/ode_e20XX/bootblock.c b/src/mainboard/bap/ode_e20XX/bootblock.c new file mode 100644 index 0000000000..8744547bfc --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/bootblock.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + pm_write8(0xea, 0x1); + + fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); +} -- cgit v1.2.3