From 8cbd569f74d8929387730e45b0d6e993b1365c02 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Fri, 1 Dec 2017 20:49:48 -0800 Subject: cavium: Add CN81xx SoC and eval board support This adds Cavium CN81xx SoC and SFF EVB files. Code is based off of Cavium's Octeon-TX SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK BDK coreboot differences: bootblock: - Get rid of BDK header - Add Kconfig for link address - Move CAR setup code into assembly - Move unaligned memory access enable into assembly - Implement custom bootblock entry function - Add CLIB and CSIB blobs romstage: - Use minimal DRAM init only devicetree: - Convert FTD to static C file containing key value pairs Tested on CN81xx: - Boots to payload - Tested with GNU/Linux 4.16.3 - All hardware is usable (after applying additional commits) Implemented in future commits: - Vboot integration - MMU suuport - L2 Cache handling - ATF from external repo - Devicetree patching - Extended DRAM testing - UART init Not working: - Booting a payload - Booting upstream ATF TODO: - Configuration straps Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688 Signed-off-by: David Hendricks Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/23037 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/mainboard/cavium/cn8100_sff_evb/board_info.txt | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 src/mainboard/cavium/cn8100_sff_evb/board_info.txt (limited to 'src/mainboard/cavium/cn8100_sff_evb/board_info.txt') diff --git a/src/mainboard/cavium/cn8100_sff_evb/board_info.txt b/src/mainboard/cavium/cn8100_sff_evb/board_info.txt new file mode 100644 index 0000000000..98a6c46b7f --- /dev/null +++ b/src/mainboard/cavium/cn8100_sff_evb/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Cavium +Board name: CN81XX SFF EVB +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: n -- cgit v1.2.3