From de7f8d3a194126d2f014668469695f26f071b48e Mon Sep 17 00:00:00 2001 From: Hal Martin Date: Sat, 28 Oct 2017 10:58:08 +0000 Subject: mainboard/compulab: add support for CompuLab Intense-PC Add coreboot support for CompuLab Intense-PC (Ivy Bridge) Modifications: - Memory SPDs have been fixed to detect both installed SODIMM modules - Full-height Mini-PCIe slot defaults to PCIe mode - mSATA can be chosen instead of mPCIe via Kconfig option ENABLE_MSATA Tested (Xubuntu 17.10/Linux 4.13 where applicable): - 2+2GB DDR3-1600 SODIMMs pass memtest - 4+4GB DDR3-1600 SODIMMs pass memtest - 4+8GB DDR3-1333 SODIMMs pass memtest - 8+8GB DDR3-1333 SODIMMs pass memtest - Booting via USB working (with no SATA HDD present) - Booting to main SATA HDD working - DisplayPort and HDMI output working for coreboot init (*requires* VGA BIOS) - DisplayPort and HDMI dual-head working in Linux - Mini-PCIe devices (half/full-height) detected in Linux - mSATA working (when chosen using ENABLE_MSATA) - Onboard Intel 82579 GbE working - Secondary Realtek 8111 GbE working - Rear eSATA ports working - Onboard analog audio output working - HDMI audio output working - USB 3.0 working - Suspend to RAM (S3) working, but not tested extensively - Mini PCIe WiFi - FACE module FM-4USB (4 USB 2.0 ports) Disabled/unsupported: - TPM (BTO option, not included in base config) - FACE modules: - FM-USB3 (USB 3.0/mSATA) NOT SUPPORTED/TESTED - FM-SER (serial) NOT SUPPORTED/TESTED - FM-XTDEU2/4 (LAN) NOT SUPPORTED/TESTED - FM-XTDE4U2/4 (Quad LAN) NOT SUPPORTED/TESTED - FM-XTDM2 (dual mPCIe) NOT SUPPORTED/TESTED - FM-VC (video capture) NOT SUPPORTED/TESTED - FM-POE (Quad LAN w/PoE) NOT SUPPORTED/TESTED Not tested: - RS-232 Product information: http://www.fit-pc.com/web/products/intense-pc/ Change-Id: I741b0b2f87eb9147c375b405a5b6989a10c7ad0a Signed-off-by: Hal Martin Reviewed-on: https://review.coreboot.org/22210 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph --- src/mainboard/compulab/intense_pc/Kconfig | 69 +++++++ src/mainboard/compulab/intense_pc/Kconfig.name | 2 + src/mainboard/compulab/intense_pc/Makefile.inc | 2 + src/mainboard/compulab/intense_pc/acpi/ec.asl | 22 +++ .../compulab/intense_pc/acpi/platform.asl | 26 +++ src/mainboard/compulab/intense_pc/acpi/superio.asl | 16 ++ src/mainboard/compulab/intense_pc/acpi_tables.c | 33 ++++ src/mainboard/compulab/intense_pc/board_info.txt | 7 + src/mainboard/compulab/intense_pc/devicetree.cb | 201 +++++++++++++++++++ src/mainboard/compulab/intense_pc/dsdt.asl | 46 +++++ src/mainboard/compulab/intense_pc/gpio.c | 219 +++++++++++++++++++++ src/mainboard/compulab/intense_pc/hda_verb.c | 88 +++++++++ src/mainboard/compulab/intense_pc/mainboard.c | 82 ++++++++ src/mainboard/compulab/intense_pc/romstage.c | 68 +++++++ 14 files changed, 881 insertions(+) create mode 100644 src/mainboard/compulab/intense_pc/Kconfig create mode 100644 src/mainboard/compulab/intense_pc/Kconfig.name create mode 100644 src/mainboard/compulab/intense_pc/Makefile.inc create mode 100644 src/mainboard/compulab/intense_pc/acpi/ec.asl create mode 100644 src/mainboard/compulab/intense_pc/acpi/platform.asl create mode 100644 src/mainboard/compulab/intense_pc/acpi/superio.asl create mode 100644 src/mainboard/compulab/intense_pc/acpi_tables.c create mode 100644 src/mainboard/compulab/intense_pc/board_info.txt create mode 100644 src/mainboard/compulab/intense_pc/devicetree.cb create mode 100644 src/mainboard/compulab/intense_pc/dsdt.asl create mode 100644 src/mainboard/compulab/intense_pc/gpio.c create mode 100644 src/mainboard/compulab/intense_pc/hda_verb.c create mode 100644 src/mainboard/compulab/intense_pc/mainboard.c create mode 100644 src/mainboard/compulab/intense_pc/romstage.c (limited to 'src/mainboard/compulab/intense_pc') diff --git a/src/mainboard/compulab/intense_pc/Kconfig b/src/mainboard/compulab/intense_pc/Kconfig new file mode 100644 index 0000000000..283d63afdb --- /dev/null +++ b/src/mainboard/compulab/intense_pc/Kconfig @@ -0,0 +1,69 @@ +if BOARD_COMPULAB_INTENSE_PC + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select CPU_INTEL_SOCKET_FCBGA1023 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config HAVE_GBE_BIN + bool + default n + +config MAINBOARD_DIR + string + default compulab/intense_pc + +config MAINBOARD_PART_NUMBER + string + default "Intense-PC" + +config VGA_BIOS_ID + string + default "8086,0166" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x7270 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x8086 + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 + +config ENABLE_MSATA # enable mSATA instead of mPCIe on full height slot + bool "Use full-height mini-PCIe for mSATA" + default n +endif diff --git a/src/mainboard/compulab/intense_pc/Kconfig.name b/src/mainboard/compulab/intense_pc/Kconfig.name new file mode 100644 index 0000000000..af04f6c18b --- /dev/null +++ b/src/mainboard/compulab/intense_pc/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_COMPULAB_INTENSE_PC + bool "Intense-PC" diff --git a/src/mainboard/compulab/intense_pc/Makefile.inc b/src/mainboard/compulab/intense_pc/Makefile.inc new file mode 100644 index 0000000000..ed24e18e84 --- /dev/null +++ b/src/mainboard/compulab/intense_pc/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-y += acpi_tables.c diff --git a/src/mainboard/compulab/intense_pc/acpi/ec.asl b/src/mainboard/compulab/intense_pc/acpi/ec.asl new file mode 100644 index 0000000000..cc80166e85 --- /dev/null +++ b/src/mainboard/compulab/intense_pc/acpi/ec.asl @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Hal Martin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/compulab/intense_pc/acpi/platform.asl b/src/mainboard/compulab/intense_pc/acpi/platform.asl new file mode 100644 index 0000000000..a726eed8f9 --- /dev/null +++ b/src/mainboard/compulab/intense_pc/acpi/platform.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Hal Martin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/compulab/intense_pc/acpi/superio.asl b/src/mainboard/compulab/intense_pc/acpi/superio.asl new file mode 100644 index 0000000000..becdf3df85 --- /dev/null +++ b/src/mainboard/compulab/intense_pc/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Hal Martin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/compulab/intense_pc/acpi_tables.c b/src/mainboard/compulab/intense_pc/acpi_tables.c new file mode 100644 index 0000000000..9d57af17e4 --- /dev/null +++ b/src/mainboard/compulab/intense_pc/acpi_tables.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2017 Hal Martin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/compulab/intense_pc/board_info.txt b/src/mainboard/compulab/intense_pc/board_info.txt new file mode 100644 index 0000000000..d533ee4cf9 --- /dev/null +++ b/src/mainboard/compulab/intense_pc/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: CompuLab +Board name: Intense-PC +Category: laptop +ROM package: SOIC-16 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb new file mode 100644 index 0000000000..8b1deb3d40 --- /dev/null +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -0,0 +1,201 @@ +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Hal Martin +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x0000164d" + register "gen2_dec" = "0x000c0681" + register "gen3_dec" = "0x000406f1" + register "gen4_dec" = "0x000c06a1" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + # Intense PC SATA portmap: + # Port 0: internal 2.5" bay + # Port 1: optional FACE module + # Port 2: rear eSATA + # Port 3: rear eSATA + # Port 4: mSATA + # Port 5: optional FACE module + # enable ALL ports (FACE module REQUIRED for ports 1&5) + register "sata_port_map" = "0x3f" + # enable ONLY ports present on stock MintBox/Intense PC + #register "sata_port_map" = "0x1d" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + + # USB 3.0 Controller + device pci 14.0 on + subsystemid 0x8086 0x7270 + end + + # Management Engine Interface 1 + device pci 16.0 off + end + + # Management Engine Interface 2 + device pci 16.1 off + end + + # Management Engine IDE-R + device pci 16.2 off + end + + # Management Engine KT + device pci 16.3 off + end + + # Intel Gigabit Ethernet + device pci 19.0 on + end + + # USB2 EHCI #2 + device pci 1a.0 on + subsystemid 0x8086 0x7270 + end + + # High Definition Audio Audio controller + device pci 1b.0 on + subsystemid 0x8086 0x7270 + end + + # PCIe Port #1 + device pci 1c.0 on + subsystemid 0x8086 0x7270 + end + + # PCIe Port #2 + device pci 1c.1 on + subsystemid 0x8086 0x7270 + end + + # PCIe Port #3 + device pci 1c.2 on + subsystemid 0x8086 0x7270 + end + + # PCIe Port #4 + device pci 1c.3 off + end + + # PCIe Port #5 + device pci 1c.4 on + subsystemid 0x8086 0x7270 + end + + # PCIe Port #6 + device pci 1c.5 off + end + + # PCIe Port #7 + device pci 1c.6 off + end + + # PCIe Port #8 + device pci 1c.7 off + end + + # USB2 EHCI #1 + device pci 1d.0 on + subsystemid 0x8086 0x7270 + end + + # PCI bridge + device pci 1e.0 off + end + + # LPC bridge PCI-LPC bridge + device pci 1f.0 on + subsystemid 0x8086 0x7270 + end + + # SATA Controller 1 + device pci 1f.2 on + subsystemid 0x8086 0x7270 + end + + # SMBus + device pci 1f.3 on + subsystemid 0x8086 0x7270 + end + + # SATA Controller 2 + device pci 1f.5 off + end + + # Thermal Unsupported PCI device 8086:1e24 + device pci 1f.6 on + subsystemid 0x8086 0x7270 + end + end + + # Host bridge Host bridge + device pci 00.0 on + subsystemid 0x8086 0x2010 + end + + # PCIe Bridge for discrete graphics PCI device 8086:0151 + device pci 01.0 on + subsystemid 0x8086 0x2010 + end + + # Internal graphics VGA controller + device pci 02.0 on + subsystemid 0x8086 0x2211 + end + + # Unsupported PCI device 8086:0155 + device pci 01.1 on + subsystemid 0x8086 0x2010 + end + end +end diff --git a/src/mainboard/compulab/intense_pc/dsdt.asl b/src/mainboard/compulab/intense_pc/dsdt.asl new file mode 100644 index 0000000000..486ad43c47 --- /dev/null +++ b/src/mainboard/compulab/intense_pc/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Hal Martin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + #include + #include + } + } +} diff --git a/src/mainboard/compulab/intense_pc/gpio.c b/src/mainboard/compulab/intense_pc/gpio.c new file mode 100644 index 0000000000..373c9f1995 --- /dev/null +++ b/src/mainboard/compulab/intense_pc/gpio.c @@ -0,0 +1,219 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + #if IS_ENABLED(CONFIG_ENABLE_MSATA) + .gpio8 = GPIO_LEVEL_LOW, + #else + .gpio8 = GPIO_LEVEL_HIGH, + #endif + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio34 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio66 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/compulab/intense_pc/hda_verb.c b/src/mainboard/compulab/intense_pc/hda_verb.c new file mode 100644 index 0000000000..5cade62e6f --- /dev/null +++ b/src/mainboard/compulab/intense_pc/hda_verb.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2017 Hal Martin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0888, /* Codec Vendor / Device ID: Realtek */ + 0x10ec0888, /* Subsystem ID */ + + 0x0000000f, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x10ec0888), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0x411110f0), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x01214120), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x411111f0), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19131), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x411111f0), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x014421f0), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x01c421f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/compulab/intense_pc/mainboard.c b/src/mainboard/compulab/intense_pc/mainboard.c new file mode 100644 index 0000000000..f91e44ae87 --- /dev/null +++ b/src/mainboard/compulab/intense_pc/mainboard.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Hal Martin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +static void mainboard_init(device_t dev) +{ + /* FIXME: trim this down or remove if necessary */ + { + int i; + const u8 dmp[256] = { + /* 00 */ 0x00, 0x28, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, + /* 08 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 18 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 28 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x36, 0x3c, 0x6e, + /* 30 */ 0xb8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 38 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, + /* 48 */ 0xff, 0x42, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 58 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 68 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x41, + /* 70 */ 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, + /* 78 */ 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, + /* 80 */ 0x28, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, + /* 88 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 98 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* a8 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* b8 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* c0 */ 0x00, 0x00, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + /* c8 */ 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, + /* d0 */ 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, + /* d8 */ 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, + /* e0 */ 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, + /* e8 */ 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, + /* f0 */ 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + /* f8 */ 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, + }; + + printk(BIOS_DEBUG, "Replaying EC dump ..."); + for (i = 0; i < 256; i++) + ec_write (i, dmp[i]); + printk(BIOS_DEBUG, "done\n"); + } + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c new file mode 100644 index 0000000000..8ef3f3e829 --- /dev/null +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Hal Martin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include "northbridge/intel/sandybridge/raminit_native.h" + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x0000164d); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0681); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000406f1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); +} + +void rcba_config(void) +{ + /* Disable devices. */ + RCBA32(0x3414) = 0x00000000; + RCBA32(0x3418) = 0x16e81fe3; + +} +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} -- cgit v1.2.3