From 5caf89b9f848bbab199e7e6bd37897f6464e4d23 Mon Sep 17 00:00:00 2001
From: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date: Tue, 3 May 2016 16:26:05 -0700
Subject: dmp/vortex86ex: Merge northbridge and southbridge into soc
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Change-Id: I16c04452d2d6c3205aea29fe8aa8fad8fc485a46
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14600
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/mainboard/dmp/vortex86ex/Kconfig       |  3 +--
 src/mainboard/dmp/vortex86ex/devicetree.cb | 18 ++++++++----------
 src/mainboard/dmp/vortex86ex/romstage.c    |  6 +++---
 3 files changed, 12 insertions(+), 15 deletions(-)

(limited to 'src/mainboard/dmp')

diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig
index f6e5d0c68e..9c4c178f69 100644
--- a/src/mainboard/dmp/vortex86ex/Kconfig
+++ b/src/mainboard/dmp/vortex86ex/Kconfig
@@ -18,8 +18,7 @@ if BOARD_DMP_EX
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select CPU_DMP_VORTEX86EX
-	select NORTHBRIDGE_DMP_VORTEX86EX
-	select SOUTHBRIDGE_DMP_VORTEX86EX
+	select SOC_DMP_VORTEX86EX
 	select HAVE_PIRQ_TABLE
 	select BOARD_ROMSIZE_KB_256
 	select ROMCC
diff --git a/src/mainboard/dmp/vortex86ex/devicetree.cb b/src/mainboard/dmp/vortex86ex/devicetree.cb
index 46dd2436f7..4106bed448 100644
--- a/src/mainboard/dmp/vortex86ex/devicetree.cb
+++ b/src/mainboard/dmp/vortex86ex/devicetree.cb
@@ -13,18 +13,16 @@
 ## GNU General Public License for more details.
 ##
 
-chip northbridge/dmp/vortex86ex			# North Bridge
+chip soc/dmp/vortex86ex			# North Bridge
 	device domain 0 on
 		device pci 0.0 on end		# Host Bridge
-		chip southbridge/dmp/vortex86ex	# South Bridge
-			device pci 7.0 on end	# ISA Bridge
-			device pci 8.0 on end	# Ethernet
-			device pci a.0 on end	# USB 1.1
-			device pci a.1 on end	# USB 2.0
-			device pci b.0 on end	# USB 1.1
-			device pci b.1 on end	# USB 2.0
-			device pci c.0 on end	# IDE
-		end
+		device pci 7.0 on end	# ISA Bridge
+		device pci 8.0 on end	# Ethernet
+		device pci a.0 on end	# USB 1.1
+		device pci a.1 on end	# USB 2.0
+		device pci b.0 on end	# USB 1.1
+		device pci b.1 on end	# USB 2.0
+		device pci c.0 on end	# IDE
 	end # pci domain 0
 	chip cpu/dmp/vortex86ex end	# CPU
 end
diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c
index a6aa59b5dc..0b02373952 100644
--- a/src/mainboard/dmp/vortex86ex/romstage.c
+++ b/src/mainboard/dmp/vortex86ex/romstage.c
@@ -22,9 +22,9 @@
 #include <cpu/x86/cache.h>
 #include <halt.h>
 #include "drivers/pc80/pc/i8254.c"
-#include <northbridge/dmp/vortex86ex/northbridge.h>
-#include <southbridge/dmp/vortex86ex/southbridge.h>
-#include "northbridge/dmp/vortex86ex/raminit.c"
+#include <soc/dmp/vortex86ex/northbridge.h>
+#include <soc/dmp/vortex86ex/southbridge.h>
+#include "soc/dmp/vortex86ex/raminit.c"
 #include <cpu/dmp/dmp_post_code.h>
 
 #define DMP_CPUID_SX      0x31504d44
-- 
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