From 466ca2c1adbf2fc97dd559a3b69fcf0c7fe5d472 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Tue, 22 Oct 2019 02:02:24 +0000 Subject: Add configurable ramstage support for minimal PCI scanning This CL has changes that allow us to enable a configurable ramstage, and one change that allows us to minimize PCI scanning. Minimal scanning is a frequently requested feature. To enable it, we add two new variables to src/Kconfig CONFIGURABLE_RAMSTAGE is the overall variable controlling other options for minimizing the ramstage. MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal PCI scanning. Some devices must be scanned in all cases, such as 0:0.0. To indicate which devices we must scan, we add a new mandatory keyword to sconfig It is used in place of on, off, or hidden, and indicates a device is enabled and mandatory. Mandatory devices are always scanned. When MINIMAL_PCI_SCANNING is enabled, ONLY mandatory devices are scanned. We further add support in src/device/pci_device.c to manage both MINIMAL_PCI_SCANNING and mandatory devices. Finally, to show how this works in practice, we add mandatory keywords to 3 devices on the qemu-q35. TEST= 1. This is tested and working on the qemu-q35 target. 2. On CML-Hatch Before CL: Total Boot time: ~685ms After CL: Total Boot time: ~615ms Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e Signed-off-by: Ronald G. Minnich Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221 Tested-by: build bot (Jenkins) Reviewed-by: Jeremy Soller --- src/mainboard/emulation/qemu-q35/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/emulation/qemu-q35/devicetree.cb') diff --git a/src/mainboard/emulation/qemu-q35/devicetree.cb b/src/mainboard/emulation/qemu-q35/devicetree.cb index 671a2d631d..c032606e67 100644 --- a/src/mainboard/emulation/qemu-q35/devicetree.cb +++ b/src/mainboard/emulation/qemu-q35/devicetree.cb @@ -5,10 +5,10 @@ chip mainboard/emulation/qemu-q35 end end device domain 0 on - device pci 0.0 on end # northbridge (q35) + device pci 0.0 mandatory end # northbridge (q35) chip southbridge/intel/i82801ix # present unconditionally - device pci 1f.0 on end # LPC + device pci 1f.0 mandatory end # LPC device pci 1f.2 on end # SATA device pci 1f.3 on end # SMBus -- cgit v1.2.3