From 035cf718229baaa7cd412824d32501b1a9d55e1d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Fri, 9 Jun 2017 14:07:20 +0200 Subject: mb/emulation/spike-riscv: Update UART address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I updated my spike patch[1] to cleanly apply to current spike master. As a side effect, the UART is now at 0x02100000. [1]: https://github.com/riscv/riscv-isa-sim/pull/53 Change-Id: I4cb09014619e230011486fa57636abe183baa4be Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/20126 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/mainboard/emulation/spike-riscv/uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/emulation') diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c index 57647fee1d..26ab630091 100644 --- a/src/mainboard/emulation/spike-riscv/uart.c +++ b/src/mainboard/emulation/spike-riscv/uart.c @@ -20,5 +20,5 @@ uintptr_t uart_platform_base(int idx) { - return (uintptr_t) 0x40001000; + return (uintptr_t) 0x02100000; } -- cgit v1.2.3