From 5f8cb140e63f30016c7289d7cb0afec77deeed48 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Thu, 7 Jul 2016 20:53:28 +0200 Subject: spike-riscv: Look for the CBFS in RAM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I98927a70adc45d9aca916bd985932b94287921de Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/15285 Reviewed-by: Ronald G. Minnich Tested-by: build bot (Jenkins) --- src/mainboard/emulation/qemu-riscv/Makefile.inc | 3 +++ src/mainboard/emulation/qemu-riscv/rom_media.c | 26 ++++++++++++++++++++ src/mainboard/emulation/spike-riscv/Makefile.inc | 3 +++ src/mainboard/emulation/spike-riscv/rom_media.c | 30 ++++++++++++++++++++++++ 4 files changed, 62 insertions(+) create mode 100644 src/mainboard/emulation/qemu-riscv/rom_media.c create mode 100644 src/mainboard/emulation/spike-riscv/rom_media.c (limited to 'src/mainboard/emulation') diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 87bc39ad2e..b8a62f79a6 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -15,11 +15,14 @@ bootblock-y += bootblock.c bootblock-y += uart.c bootblock-y += qemu_util.c +bootblock-y += rom_media.c romstage-y += romstage.c romstage-y += qemu_util.c romstage-y += uart.c +romstage-y += rom_media.c ramstage-y += uart.c ramstage-y += qemu_util.c +ramstage-y += rom_media.c bootblock-y += memlayout.ld romstage-y += memlayout.ld diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c new file mode 100644 index 0000000000..c1713074f9 --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +/* This assumes that the CBFS resides at 0x0, which is true for the default + * configuration. */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index dff4758173..91c136924e 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -15,11 +15,14 @@ bootblock-y += bootblock.c bootblock-y += uart.c bootblock-y += spike_util.c +bootblock-y += rom_media.c romstage-y += romstage.c romstage-y += uart.c romstage-y += spike_util.c +romstage-y += rom_media.c ramstage-y += uart.c ramstage-y += spike_util.c +ramstage-y += rom_media.c bootblock-y += memlayout.ld romstage-y += memlayout.ld diff --git a/src/mainboard/emulation/spike-riscv/rom_media.c b/src/mainboard/emulation/spike-riscv/rom_media.c new file mode 100644 index 0000000000..10952a39ee --- /dev/null +++ b/src/mainboard/emulation/spike-riscv/rom_media.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright 2016 Jonathan Neuschäfer + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +/* + * 0x80000000 is this start of RAM. We currently need to load coreboot.rom into + * RAM on SPIKE, because SPIKE doesn't support loading custom code into the + * boot ROM. + */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT(0x80000000, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} -- cgit v1.2.3