From b451df2f400ba12fff440247330f8b57a93034bd Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 15 Aug 2017 20:59:09 +0200 Subject: mb/*/*/romstage.c: Clean up targets with i82801gx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Things cleaned up in this patch: * Add macros for the GENx_DEC registers; * replace many magic numbers by macros; * remove many writes to DxxIP since they were 'setting' reset default values; * fix some comments about decode ranges. Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/21065 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) (limited to 'src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c') diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 9789d2acf6..926a5a7f36 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -68,27 +68,29 @@ static void setup_sio(void) static void ich7_enable_lpc(void) { // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0000); // Enable COM1 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340d); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN + | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMA_LPC_EN); // Enable SuperIO Power Management Events - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0801); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0801); /* LPC decode range 2: Environment Controller */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040291); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00040291); } static void rcba_config(void) { /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; + RCBA8(OIC) = 0x03; /* Disable unused devices */ - RCBA32(0x3418) = 0x003c0061; + RCBA32(FD) = 0x003c0061; /* Enable PCIe Root Port Clock Gate */ - RCBA32(0x341c) = 0x00000001; + RCBA32(CG) = 0x00000001; } static void early_ich7_init(void) @@ -123,14 +125,14 @@ static void early_ich7_init(void) RCBA32(0x0214) = 0x10030509; RCBA32(0x0218) = 0x00020504; RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); + reg32 = RCBA32(GCS); reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; + RCBA32(GCS) = reg32; reg32 = RCBA32(0x3430); reg32 &= ~(3 << 0); reg32 |= (1 << 0); RCBA32(0x3430) = reg32; - RCBA32(0x3418) |= (1 << 0); + RCBA32(FD) |= (1 << 0); RCBA16(0x0200) = 0x2008; RCBA8(0x2027) = 0x0d; RCBA16(0x3e08) |= (1 << 7); -- cgit v1.2.3