From 62902ca45de871aa59657dd8ec1858c301595634 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 29 Nov 2016 14:13:43 +0100 Subject: sb/ich7: Use common/gpio.h to set up GPIOs This is more consistent with newer Intel targets. This a static struct so it is initialized to 0 by default. To make it more readable: * only setting to GPIO mode is made explicit; * only pins in GPIO mode are either set to input or output since this is ignored in native mode; * only output pins are set high or low, since this is read-only on input; * blink is only operational on output pins, non-blink is not set explicitly; * invert is only operational on input pins, non-invert is not set explicitly. Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/17639 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel --- src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc | 1 + src/mainboard/gigabyte/ga-g41m-es2l/gpio.c | 117 +++++++++++++++++++++++ src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 10 +- 3 files changed, 120 insertions(+), 8 deletions(-) create mode 100644 src/mainboard/gigabyte/ga-g41m-es2l/gpio.c (limited to 'src/mainboard/gigabyte/ga-g41m-es2l') diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc index f9621db6b3..f3d7e76263 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc @@ -1 +1,2 @@ ramstage-y += cstates.c +romstage-y += gpio.c diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/gpio.c b/src/mainboard/gigabyte/ga-g41m-es2l/gpio.c new file mode 100644 index 0000000000..e06a8f1ec9 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/gpio.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Arthur Heymans + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 2503db9433..0f437951e5 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -50,14 +51,7 @@ static void mb_gpio_init(void) pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); pci_write_config8(dev, GPIO_CNTL, 0x10); - outl(0x1f35f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ - outl(0xe2e9ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0xe0d7ec02, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ - outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ - outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ - outl(0x000000e7, DEFAULT_GPIOBASE + 0x30); - outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); - outl(0x00000083, DEFAULT_GPIOBASE + 0x38); + setup_pch_gpios(&mainboard_gpio_map); /* Set default GPIOs on superio */ ite_reg_write(GPIO_DEV, 0x25, 0x00); -- cgit v1.2.3