From 12aba82e55c02470ed80b7682efa8b4e8f702bc1 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 30 Apr 2009 07:07:22 +0000 Subject: Refactor copy_and_run so that it uses a single code base instead of 3 (with one of them way too much assembler code). On the way, I had to make some changes to the way the code is built, which is an effort I want to expand over time. Right now, large portions of the in-ROM part of coreboot is compiled as a single file, with lots of .c files including other .c files. That has its justification for pre-raminit code, but it also affects lots of post-raminit code (memcpy doesn't really make sense before raminit, or at least CAR) The coreboot_apc code (AMD boards) gained some .c includes because I don't know that part of the code enough to really rework it and only have limited possibilities to test it. The includes should give an identical situation for this part of the code. This change was posted as set of 6 patches to the list, but they were mostly split for review purposes, hence commit them all at once. They can still be backed up using the patch files, if necessary. Signed-off-by: Patrick Georgi Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'src/mainboard/gigabyte/m57sli') diff --git a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c index fb52c86c24..5462c31891 100644 --- a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c +++ b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c @@ -46,6 +46,7 @@ #define DBGP_DEFAULT 7 #include +#include #include #include #include @@ -82,10 +83,6 @@ #include "cpu/x86/bist.h" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" -- cgit v1.2.3