From 5dd4bf3644e13ad65edf2244ea672850a40e95e4 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Mon, 23 Dec 2019 13:53:56 +0800 Subject: mb/gigabyte/ga-b75m-d3h: enable superspeed ports for all variants Unlike other Panther Point boards, the ga-b75m-d3h lacks definitions to wire SuperSpeed-capable ports to XHCI in its devicetree, causing these ports being wired to the second EHCI, and only working as USB 2.0 ports. The missing register definitions are added to fix that. Tested on my ga-b75-d3v board. Change-Id: Ida4de26f1a493ead83065b1ab27c0c684a074513 Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/37912 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/gigabyte') diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 57b4960a12..7b470677b0 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -38,6 +38,9 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x3f" register "sata_interface_speed_support" = "0x3" + register "xhci_switchable_ports" = "0xf" + register "superspeed_capable_ports" = "0xf" + register "pcie_port_coalesce" = "0" register "docking_supported" = "0" register "c2_latency" = "0x0065" -- cgit v1.2.3