From 6798b478027cb3fd44d52706ad69dee29bae19ba Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Thu, 7 Oct 2010 16:24:28 +0000 Subject: Convert all Intel 82371AB/EB/MB based boards to TINY_BOOTBLOCK. Also: Unfortunately Intel 440BX + 82371AB/EB/MB boards can have their ISA device on various PCI bus:device.function locations. Examples we encountered: 00:07.0, 00:04.0, or 00:14.0. Thus, instead of hardcoding PCI bus:device.function numbers such as PCI_DEV(0, 7, 0), we now simply find the ISA device via PCI IDs, which works the same on all boards. As an additional benefit this patch also gets rid of one .c file include in romstage.c. Abuild-tested. Signed-off-by: Uwe Hermann Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/gigabyte/ga-6bxc/romstage.c | 4 ---- src/mainboard/gigabyte/ga-6bxe/romstage.c | 4 ---- 2 files changed, 8 deletions(-) (limited to 'src/mainboard/gigabyte') diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index 040e762d24..13e1ff71d3 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -26,7 +26,6 @@ #include #include #include -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -54,9 +53,6 @@ void main(unsigned long bist) console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index aafd39453c..e60ca46fa8 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -26,7 +26,6 @@ #include #include #include -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -55,9 +54,6 @@ void main(unsigned long bist) console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); -- cgit v1.2.3