From 77757c22b9eede92234d07d65a23fdf4b970c8cf Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Sun, 4 Jan 2015 21:33:39 +1100 Subject: mainboard/*/romstage.c: Sanitize system header inclusions Fix system include paths to be consistent. Chipset support is part of the Coreboot 'system' and hence 'non-local' (i.e., in the same directory or context). One possible product of this, is to perhaps allow future work to do pre-compiled headers (PCH) on the buildbot for faster build times. However, this currently just makes mainboard's consistent. Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5 Signed-off-by: Edward O'Callaghan Reviewed-on: http://review.coreboot.org/8085 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/mainboard/gigabyte/ga-6bxc/romstage.c | 6 +++--- src/mainboard/gigabyte/ga-6bxe/romstage.c | 6 +++--- src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 8 ++++---- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 12 ++++++------ src/mainboard/gigabyte/m57sli/romstage.c | 10 +++++----- src/mainboard/gigabyte/ma785gm/romstage.c | 16 ++++++++-------- src/mainboard/gigabyte/ma785gmt/romstage.c | 16 ++++++++-------- src/mainboard/gigabyte/ma78gm/romstage.c | 16 ++++++++-------- 8 files changed, 45 insertions(+), 45 deletions(-) (limited to 'src/mainboard/gigabyte') diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index 9e465dd071..3897551e60 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -24,11 +24,11 @@ #include #include #include -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include +#include #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include #include #include diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index 369a23f0f3..995a65723c 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -24,11 +24,11 @@ #include #include #include -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include +#include #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include #include #include diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index 6fea437c32..a1515eec04 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -30,10 +30,10 @@ #include #include #include -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include +#include +#include +#include #include #include diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 10bbb6f361..44fa4ca6b0 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -32,15 +32,15 @@ #include #include #include -#include "southbridge/sis/sis966/sis966.h" +#include #include "southbridge/sis/sis966/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include #include "northbridge/amd/amdk8/reset_test.c" #include #include -#include "cpu/x86/bist.h" +#include #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/sis/sis966/early_ctrl.c" @@ -56,7 +56,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" @@ -78,7 +78,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/sis/sis966/early_setup_ss.h" +#include #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index b2e1d70477..da12a97c69 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -31,13 +31,13 @@ #include #include #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include #include "northbridge/amd/amdk8/reset_test.c" #include #include -#include "cpu/x86/bist.h" +#include #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -61,9 +61,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include #include "southbridge/nvidia/mcp55/early_setup_car.c" -#include "northbridge/amd/amdk8/f.h" +#include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 75090d9136..8d73b265fa 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -30,20 +30,20 @@ #include #include #include -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include +#include #include -#include "cpu/x86/lapic.h" +#include #include "northbridge/amd/amdfam10/reset_test.c" #include -#include "cpu/x86/bist.h" +#include #include #include #include #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include +#include #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) @@ -56,12 +56,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 87778c6fca..c7094ae57f 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -30,20 +30,20 @@ #include #include #include -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include +#include #include -#include "cpu/x86/lapic.h" +#include #include "northbridge/amd/amdfam10/reset_test.c" #include -#include "cpu/x86/bist.h" +#include #include #include #include #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include +#include #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) @@ -56,12 +56,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index b3ae3266b9..bbfe80b1e5 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -34,20 +34,20 @@ #include #include #include -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include +#include #include -#include "cpu/x86/lapic.h" +#include #include "northbridge/amd/amdfam10/reset_test.c" #include -#include "cpu/x86/bist.h" +#include #include #include #include #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include +#include #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) @@ -60,12 +60,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" -- cgit v1.2.3