From a86e401c0ee0ee9440788913bf299410df92f9ef Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 24 Feb 2019 19:54:15 +0100 Subject: mb/gigabyte/ga-h61m-s2pv: fix cosmetic things Remove unneeded options, note where usbdebug is, reorder devicetree and clean up dsdt. Tested, board still boots. Change-Id: Ice0eff7b9829816aff4d334f4ac4a2fb435a2fb0 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/31558 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig | 10 +--------- src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb | 9 +++------ src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl | 17 ++++++++--------- 3 files changed, 12 insertions(+), 24 deletions(-) (limited to 'src/mainboard/gigabyte') diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig index 39a70f8896..5fba47a90f 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig @@ -40,14 +40,6 @@ config MAINBOARD_PART_NUMBER string default "GA-H61M-S2PV" -config VGA_BIOS_FILE - string - default "pci8086,0102.rom" - -config VGA_BIOS_ID - string - default "8086,0102" - config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x5001 @@ -60,7 +52,7 @@ config MAX_CPUS int default 8 -config USBDEBUG_HCD_INDEX # FIXME: check this +config USBDEBUG_HCD_INDEX # Bottom left port seen from rear int default 2 diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb index 667dd9c0b3..e382cbde7f 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb @@ -30,12 +30,12 @@ chip northbridge/intel/sandybridge end register "pci_mmio_size" = "2048" device domain 0x0 on + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics (PCIEX16) + device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" - register "docking_supported" = "0" register "gen1_dec" = "0x003c0a01" - register "p_cnt_throttling_supported" = "0" - register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" @@ -100,8 +100,5 @@ chip northbridge/intel/sandybridge device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 off end # Thermal end - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics (PCIEX16) - device pci 02.0 on end # Internal graphics VGA controller end end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl index 6a929d073e..dbf8c96f51 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl @@ -14,7 +14,9 @@ */ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + #include + DefinitionBlock( "dsdt.aml", "DSDT", @@ -24,7 +26,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/mainboard.asl" #include "acpi/platform.asl" #include "acpi/superio.asl" @@ -32,16 +33,14 @@ DefinitionBlock( #include #include - /* global NVS and variables. */ + /* global NVS and variables. */ #include #include - Scope (\_SB) { - Device (PCI0) - { - #include - #include - #include - } + Device (\_SB.PCI0) + { + #include + #include + #include } } -- cgit v1.2.3