From d862121fbe6285be2f91a0c09058a22a775c0d19 Mon Sep 17 00:00:00 2001
From: Marc Jones <marc.jones@se-eng.com>
Date: Tue, 9 Jun 2015 21:18:38 -0600
Subject: google/auron: Add mainboard

Add the Google Auron Broadwell Reference Mainboard. It is based
on the Google Peppy mainboard. It was merged from the following
chromium.org commit:  d20a1d1a22d64546a5d8761b18ab29732ec0b848

Change-Id: I716a79e198e91c428bd965fcd03665c2c7067602
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10500
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
---
 src/mainboard/google/auron/acpi_tables.c | 42 ++++++--------------------------
 1 file changed, 8 insertions(+), 34 deletions(-)

(limited to 'src/mainboard/google/auron/acpi_tables.c')

diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c
index 47288aa7db..540fe44032 100644
--- a/src/mainboard/google/auron/acpi_tables.c
+++ b/src/mainboard/google/auron/acpi_tables.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -29,27 +29,16 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
-#include <cpu/x86/msr.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-#include <ec/google/chromeec/ec.h>
-
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
 #include "thermal.h"
 
+extern const unsigned char AmlCode[];
+
 static void acpi_update_thermal_table(global_nvs_t *gnvs)
 {
 	gnvs->tmps = CTL_TDP_SENSOR_ID;
 
-	/* Normal TDP */
-	gnvs->f1of = 0;
-	gnvs->f1on = 0;
-
-	/* Limited TDP */
-	gnvs->f0of = CTL_TDP_THRESHOLD_OFF;
-	gnvs->f0on = CTL_TDP_THRESHOLD_ON;
-	gnvs->f0pw = CTL_TDP_POWER_LIMIT;
-
 	gnvs->tcrt = CRITICAL_TEMPERATURE;
 	gnvs->tpsv = PASSIVE_TEMPERATURE;
 	gnvs->tmax = MAX_TEMPERATURE;
@@ -58,22 +47,13 @@ static void acpi_update_thermal_table(global_nvs_t *gnvs)
 
 void acpi_create_gnvs(global_nvs_t *gnvs)
 {
+	acpi_init_gnvs(gnvs);
+
 	/* Enable USB ports in S3 */
 	gnvs->s3u0 = 1;
-	gnvs->s3u1 = 1;
 
 	/* Disable USB ports in S5 */
 	gnvs->s5u0 = 0;
-	gnvs->s5u1 = 0;
-
-	/* TPM Present */
-	gnvs->tpmp = 1;
-
-
-#if CONFIG_CHROMEOS
-	gnvs->chromeos.vbt2 = google_ec_running_ro() ?
-		ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
-#endif
 
 	acpi_update_thermal_table(gnvs);
 }
@@ -87,11 +67,5 @@ unsigned long acpi_fill_madt(unsigned long current)
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
 				2, IO_APIC_ADDR, 0);
 
-	/* INT_SRC_OVR */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
-	return current;
+	return acpi_madt_irq_overrides(current);
 }
-- 
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