From d862121fbe6285be2f91a0c09058a22a775c0d19 Mon Sep 17 00:00:00 2001
From: Marc Jones <marc.jones@se-eng.com>
Date: Tue, 9 Jun 2015 21:18:38 -0600
Subject: google/auron: Add mainboard

Add the Google Auron Broadwell Reference Mainboard. It is based
on the Google Peppy mainboard. It was merged from the following
chromium.org commit:  d20a1d1a22d64546a5d8761b18ab29732ec0b848

Change-Id: I716a79e198e91c428bd965fcd03665c2c7067602
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10500
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
---
 src/mainboard/google/auron/dsdt.asl | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

(limited to 'src/mainboard/google/auron/dsdt.asl')

diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl
index 76998ba670..1c10f80da3 100644
--- a/src/mainboard/google/auron/dsdt.asl
+++ b/src/mainboard/google/auron/dsdt.asl
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,8 +18,6 @@
  * Foundation, Inc.
  */
 
-#define ENABLE_TPM
-
 DefinitionBlock(
 	"dsdt.aml",
 	"DSDT",
@@ -30,23 +28,22 @@ DefinitionBlock(
 )
 {
 	// Some generic macros
-	#include "acpi/platform.asl"
-	#include "acpi/mainboard.asl"
+	#include <soc/intel/broadwell/acpi/platform.asl>
 
 	// global NVS and variables
-	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+	#include <soc/intel/broadwell/acpi/globalnvs.asl>
 
 	// General Purpose Events
 	//#include "acpi/gpe.asl"
 
 	// CPU
-	#include <cpu/intel/haswell/acpi/cpu.asl>
+	#include <soc/intel/broadwell/acpi/cpu.asl>
 
 	Scope (\_SB) {
 		Device (PCI0)
 		{
-			#include <northbridge/intel/haswell/acpi/haswell.asl>
-			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+			#include <soc/intel/broadwell/acpi/systemagent.asl>
+			#include <soc/intel/broadwell/acpi/pch.asl>
 		}
 	}
 
@@ -58,5 +55,8 @@ DefinitionBlock(
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states
-	#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
+	#include <soc/intel/broadwell/acpi/sleepstates.asl>
+
+	// Mainboard specific
+	#include "acpi/mainboard.asl"
 }
-- 
cgit v1.2.3