From 157b189f6b97b6e9ecd8d29edbbd045fbbc231f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 16 Aug 2019 14:02:25 +0300 Subject: cpu/intel: Enter romstage without BIST MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/google/beltino/romstage.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mainboard/google/beltino') diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 70a8c1928a..d36971fc39 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -67,7 +67,7 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -130,7 +130,6 @@ void mainboard_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, }; /* Early SuperIO setup */ -- cgit v1.2.3