From 4276050d13cb8c555f0375d4ec44d33ab5d58402 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 25 Jul 2020 13:44:34 +0200 Subject: mb/*/*/devicetree.cb: Normalize disabled PIRQ values If bit 7 of a PIRQ route is set, it is disabled. Modern OSes don't use PIRQ routing, so we might as well zero the other bits for consistency. Tested on Asrock B85M Pro4 with SeaBIOS 1.13.0, still boots. Change-Id: I78980b9ea5e878a6200df0f6c18c5e7d06a7950a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43861 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/google/beltino/devicetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mainboard/google/beltino') diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 304f3cf38f..171b93f81d 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -36,10 +36,10 @@ chip northbridge/intel/haswell device pci 03.0 on end # mini-hd audio chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" + register "pirqa_routing" = "0x80" + register "pirqb_routing" = "0x80" + register "pirqc_routing" = "0x80" + register "pirqd_routing" = "0x80" register "pirqe_routing" = "0x80" register "pirqf_routing" = "0x80" register "pirqg_routing" = "0x80" -- cgit v1.2.3