From 31769d99da7f97150ddc30174c7cc315ca6e7b1f Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 30 Apr 2015 01:19:16 -0500 Subject: cpu/intel/haswell: remove dependency on socket_rpga989 Remove dependency of Haswell on cpu/intel/socket_rpga989 code, which is a carry-over from Sandy Bridge/Ivy Bridge and older coreboot conventions where features were structured around socket types. Add CPU-specific options to Kconfig and required subdirs to Makefile.inc which are curently included with socket_rpga989. TEST=successfully built and booted on google/panther Change-Id: Ic788e2928df107d11ea2d2eca7613490aaed395c Signed-off-by: Matt DeVillier Reviewed-on: http://review.coreboot.org/10037 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/bolt/Kconfig | 2 +- src/mainboard/google/bolt/devicetree.cb | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'src/mainboard/google/bolt') diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index c901b8f6dd..1ec399e910 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -2,7 +2,7 @@ if BOARD_GOOGLE_BOLT config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/bolt/devicetree.cb b/src/mainboard/google/bolt/devicetree.cb index f514bb4ff7..1d1eab52a9 100644 --- a/src/mainboard/google/bolt/devicetree.cb +++ b/src/mainboard/google/bolt/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end -- cgit v1.2.3