From a85f3ae852fcca022fe409fb96bd293ab7a8b9f9 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 5 Nov 2015 17:08:25 -0800 Subject: google/chell: Add SPD for new memory type This adds the SPD for SK-Hynix H9CCNNNCLTMLAR memory to be used in the EVT build. BUG=chrome-os-partner:47346 BRANCH=none TEST=emerge-chell coreboot Change-Id: I45d0840e43ed81d8286b005f0a99b014b7f0cf28 Signed-off-by: Patrick Georgi Original-Commit-Id: 1e917440141c586cb370147f9c5b782d6e77ea10 Original-Change-Id: I02f1349f38d83f4a09887adf81384b5a8f475dd0 Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/311214 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/12391 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/chell/spd/Makefile.inc | 1 + .../chell/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 src/mainboard/google/chell/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex (limited to 'src/mainboard/google/chell') diff --git a/src/mainboard/google/chell/spd/Makefile.inc b/src/mainboard/google/chell/spd/Makefile.inc index c5d286a39a..6e3448fcfb 100644 --- a/src/mainboard/google/chell/spd/Makefile.inc +++ b/src/mainboard/google/chell/spd/Makefile.inc @@ -23,6 +23,7 @@ SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCF # 0b0000 SPD_SOURCES += samsung_dimm_K4E6E304EE-EGCF # 0b0001 SPD_SOURCES += hynix_dimm_H9CCNNN8GTMLAR # 0b0010 SPD_SOURCES += hynix_dimm_H9CCNNNBJTMLAR # 0b0011 +SPD_SOURCES += hynix_dimm_H9CCNNNCLTMLAR # 0b0100 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/chell/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex b/src/mainboard/google/chell/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex new file mode 100644 index 0000000000..df2819f1ec --- /dev/null +++ b/src/mainboard/google/chell/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex @@ -0,0 +1,19 @@ +# SK Hynix H9CCNNNCLTMLAR-NUD_178b_QDP LPDDR3 +# 8Gb die (256Mx16), x32 @ 1866 (14-15-15-34) +# 2 rank per channel, 2 SDRAMs per rank, 4x16Gb = 8GB per channel +91 20 F1 03 05 1A 05 0A 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 80 CA FA 00 00 00 A8 00 08 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 55 00 00 00 00 00 +48 39 43 43 4E 4E 4E 43 4C 54 4D 4C 41 52 2D 4E +55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- cgit v1.2.3