From 233ae1919b72434ca6cd783c9a946d32953bc7e9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 11 Dec 2020 17:20:16 +0100 Subject: soc/intel/braswell: Clean up devicetree settings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove unreferenced settings and factor out common settings. Many of these are not mainboard-specific, and all boards use the same value. Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Frans Hendriks Reviewed-by: Michał Żygowski Reviewed-by: Furquan Shaikh --- src/mainboard/google/cyan/devicetree.cb | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'src/mainboard/google/cyan') diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index 91e9795f9b..cec1682ed1 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -7,14 +7,9 @@ chip soc/intel/braswell # Set the parameters for MemoryInit ############################################################ - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" register "PcdDvfsEnable" = "1" register "PcdCaMirrorEn" = "1" @@ -40,9 +35,6 @@ chip soc/intel/braswell register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "SVID_PMIC_CONFIG" register "PcdEmmcMode" = "PCH_PCI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" register "PcdEnableSata" = "0" # Disable SATA register "Usb2Port0PerPortPeTxiSet" = "7" register "Usb2Port0PerPortTxiSet" = "5" @@ -68,9 +60,7 @@ chip soc/intel/braswell register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM register "PMIC_I2CBus" = "1" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" -- cgit v1.2.3