From 119ace0908b66b718c4b581423309648b10e4bf7 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 2 Oct 2019 16:02:06 +0200 Subject: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented Allow configuring FSP option PcieRpSlotImplemented. Also, update all related devicetrees and configure PcieRpSlotImplemented to keep the current behaviour. Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c Signed-off-by: Nico Huber Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/google/drallion') diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 4011693d34..851248d77d 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -444,12 +444,14 @@ chip soc/intel/cannonlake device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + register "PcieRpSlotImplemented[8]" = "1" end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + register "PcieRpSlotImplemented[12]" = "1" end # PCI Express Port 13 (x4) device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 -- cgit v1.2.3