From bcfcfa4473357eb6272bc8bcc5e03f4ba517bcd2 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 3 Jun 2013 10:41:12 -0700 Subject: haswell: Update pei_data to match ref code - Add a new USB location field - Add a new "ddr_refresh_2x" field, enabled on Falco only - Fix copy+paste bug in baskingridge Checked that tREFI is halved during memory setup in the memory training log: tREFImin = 6240 << DEFAULT C(0).tREFI = 0xc30 << MODIFIED (=3120) C(0).tREFI = 0xc30 << MODIFIED (=3120) Also ensure that the SD card is detected properly again. Change-Id: Ie3a82c08df06ada9af56282b5255caefa56487f2 Signed-off-by: Duncan Laurie Reviewed-on: https://gerrit.chromium.org/gerrit/57349 Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/4219 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/mainboard/google/falco/romstage.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) (limited to 'src/mainboard/google/falco/romstage.c') diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c index 74ace9b75a..e284491bbd 100644 --- a/src/mainboard/google/falco/romstage.c +++ b/src/mainboard/google/falco/romstage.c @@ -129,17 +129,27 @@ void mainboard_romstage_entry(unsigned long bist) // 3 = disable dimm 0+1 on channel dimm_channel0_disabled: 2, dimm_channel1_disabled: 2, + // Enable 2x refresh mode + ddr_refresh_2x: 1, max_ddr3_freq: 1600, usb2_ports: { - /* Length, Enable, OCn# */ - { 0x0040, 1, 0 }, /* P0: Port A, CN8 */ - { 0x0040, 1, 0 }, /* P1: Port B, CN9 */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P4: LTE */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P5: TOUCH */ - { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */ - { 0x0040, 1, 3 }, /* P7: USB2 Port */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, /* P0: Port A, CN8 */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, /* P1: Port B, CN9 */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */ + USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ + USB_PORT_FLEX }, + { 0x0040, 1, 3, /* P7: USB2 Port */ + USB_PORT_FRONT_PANEL }, }, usb3_ports: { /* Enable, OCn# */ -- cgit v1.2.3