From 116aa3a1900dae2beb56f381e91c9890c1e8ca30 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 28 May 2013 07:55:02 -0700 Subject: falco: Add panel power sequence timings These are placeholder values until we can configure for the exact panel. Change-Id: If40367c0e5f80d46d085c89b0edae60f1ccacdaf Signed-off-by: Duncan Laurie Reviewed-on: https://gerrit.chromium.org/gerrit/56808 Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/4197 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/mainboard/google/falco/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/mainboard/google/falco') diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb index fc6462c2a2..b9bc47fb17 100644 --- a/src/mainboard/google/falco/devicetree.cb +++ b/src/mainboard/google/falco/devicetree.cb @@ -13,6 +13,14 @@ chip northbridge/intel/haswell register "gpu_cpu_backlight" = "0x00000200" register "gpu_pch_backlight" = "0x04000000" + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end -- cgit v1.2.3