From 73031bcce071f6e760cc0655200dd3be2f39c8b7 Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Tue, 14 Nov 2017 11:38:01 +0800 Subject: google/fizz: correct memory rcomp settings Follow the schematic and Doc 573387 to correct the rcomp and rcomp target settings for fizz TEST= boot ok and the system can enter and resume from S3. Change-Id: Iffa90461509cfadaca20e335a6655e549e79e749 Signed-off-by: Kane Chen Reviewed-on: https://review.coreboot.org/22479 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/mainboard/google/fizz/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google/fizz') diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c index 405c4c18b4..335662ef6d 100644 --- a/src/mainboard/google/fizz/romstage.c +++ b/src/mainboard/google/fizz/romstage.c @@ -24,9 +24,9 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; /* Rcomp resistor */ - const u16 rcomp_resistor[] = { 200, 81, 162 }; + const u16 rcomp_resistor[] = { 121, 81, 100 }; /* Rcomp target */ - const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; + const u16 rcomp_target[] = { 100, 40, 20, 20, 26 }; /* SPD was saved in S0/S5 path, skips it when resumes from S3 */ if (arch_upd->BootMode == FSP_BOOT_ON_S3_RESUME) -- cgit v1.2.3