From fe1b40b1ddbdb1ca2fdc4d66d4c3a1d7c758b76a Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Fri, 8 Feb 2019 00:29:00 +0530 Subject: mb/google/hatch: Enable DPTF functionality Enable DPTF functionality on hatch platform. Change-Id: If9ef74364616f95b27b73c39fea42d2623d78ae2 Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/c/31276 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mainboard/google/hatch/variants/baseboard/devicetree.cb') diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index eb528f25f1..aaef66365b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -57,6 +57,11 @@ chip soc/intel/cannonlake register "speed_shift_enable" = "1" # Enable S0ix register "s0ix_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "44" + register "Device4Enable" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 -- cgit v1.2.3