From 9ea70c02cd0e5e28f38136ebbb6dbad72ad177c7 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 12 Oct 2019 15:16:33 +0200 Subject: intel/cannonlake: Implement PCIe RP devicetree update Some existing devicetrees were manually adapted to anticipate root-port switching. Now, their PCI-device on/off settings should just reflect the `PcieRpEnable` state and configuration happens on the PCI function that was assigned at reset. Change-Id: I4d76f38c222b74053c6a2f80b492d4660ab4db6d Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36651 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Patrick Rudolph Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons --- src/mainboard/google/hatch/variants/duffy/overridetree.cb | 5 ++--- src/mainboard/google/hatch/variants/kaisa/overridetree.cb | 5 ++--- src/mainboard/google/hatch/variants/puff/overridetree.cb | 5 ++--- 3 files changed, 6 insertions(+), 9 deletions(-) (limited to 'src/mainboard/google/hatch') diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb index d7acbd71e7..4e7692c1e9 100644 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -294,7 +294,7 @@ chip soc/intel/cannonlake end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1c.0 on + device pci 1c.6 on chip drivers/net register "customized_leds" = "0x05af" register "wake" = "GPE0_DW1_07" # GPP_C7 @@ -305,8 +305,7 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end - end # FSP requires func0 be enabled. - device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). + end # RTL8111H Ethernet NIC device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index f5e85bde23..c7655ac5c1 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -294,7 +294,7 @@ chip soc/intel/cannonlake end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1c.0 on + device pci 1c.6 on chip drivers/net register "customized_leds" = "0x05af" register "wake" = "GPE0_DW1_07" # GPP_C7 @@ -305,8 +305,7 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end - end # FSP requires func0 be enabled. - device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). + end # RTL8111H Ethernet NIC device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 31efc4a1d9..83fcf9a76c 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -297,7 +297,7 @@ chip soc/intel/cannonlake end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1c.0 on + device pci 1c.6 on chip drivers/net register "customized_leds" = "0x05af" register "wake" = "GPE0_DW1_07" # GPP_C7 @@ -308,8 +308,7 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end - end # FSP requires func0 be enabled. - device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). + end # RTL8111H Ethernet NIC device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) device pci 1e.3 off end # GSPI #1 end -- cgit v1.2.3