From c325fa1312ed2cbbfcb7ba6cb395146120701e7e Mon Sep 17 00:00:00 2001
From: Shelley Chen <shchen@google.com>
Date: Wed, 20 Mar 2019 13:48:00 -0700
Subject: mb/google/hatch: Add overridetree to hatch variant

Add serialio settings to hatch.  Only applies to CML.

BUG=b:128347800
BRANCH=None
TEST=abuild

Change-Id: I6a9ec778d74cd48a2e1c79f8e669a9a6a6a9477d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32003
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/hatch/Kconfig                     |  4 ++++
 .../google/hatch/variants/hatch/overridetree.cb        | 18 ++++++++++++++++++
 2 files changed, 22 insertions(+)
 create mode 100644 src/mainboard/google/hatch/variants/hatch/overridetree.cb

(limited to 'src/mainboard/google/hatch')

diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index f632a02d03..19c71841b2 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -80,6 +80,10 @@ config MAX_CPUS
 	int
 	default 8
 
+config OVERRIDE_DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_HATCH_WHL
+
 config TPM_TIS_ACPI_INTERRUPT
 	int
 	default 53 # GPE0_DW1_21 (GPP_C21)
diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb
new file mode 100644
index 0000000000..6e6414e8a8
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb
@@ -0,0 +1,18 @@
+chip soc/intel/cannonlake
+
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+		[PchSerialIoIndexSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexSPI1] = PchSerialIoPci,
+		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+end
-- 
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