From eaee392cb323e2d4e9e6fd985dda4a0bbbeb5b87 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 29 Jul 2019 14:35:03 +0530 Subject: mb/google/hatch: Enable PmTimerDisabled config to reduce S0ix power usage BRANCH=none BUG=b:138152075 TEST=Build for cometlake board with the PmTimerDisabled policy in devicetree set to 1. With PmTimerDisabled = 0 >> iotools mmio_read8 0xfe0018fc 0x00 With PmTimerDisabled = 1 >> iotools mmio_read8 0xfe0018fc 0x02 Bit 1: ACPI Timer Disable (ACPI_TIM_DIS): This bit determines whether the ACPI Timer is enabled to run. - 0: ACPI Timer is enabled - 1: ACPI Timer is disabled Change-Id: I83f49505a804c99d7978e5d541ea9fe8ead9b88f Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/34611 Tested-by: build bot (Jenkins) Reviewed-by: Aamir Bohra Reviewed-by: V Sowmya --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/google/hatch') diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 14630a4ace..00198a5a81 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -52,6 +52,8 @@ chip soc/intel/cannonlake # putting it under register "common_soc_config" in overridetree.cb file. register "common_soc_config.pch_thermal_trip" = "77" + register "PmTimerDisabled" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | -- cgit v1.2.3