From 0148fcb4e1d1c4e43cd21e7b28a65afd762daa6d Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sat, 17 Dec 2016 17:13:23 -0600 Subject: Combine Broadwell Chromeboxes using variant board scheme Combine existing boards google/guado, rikku, and tidus using their common reference board google/jecht as a base. Additional changes besides simple consolidation include: - simplify power LED functions - simplify HDA verb definitions using azelia macros - use common SoC functions to generate FADT table - correct FADT table header version - remove unused haswell_pci_irqs.asl - remove unused header includes (various) - set sane default fan speed (0x4d) for all variants Variant setup modeled after google/beltino Change-Id: I77a2dffe9601734916a33fd04ead98016ad0bc4b Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/17913 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/google/jecht/devicetree.cb | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'src/mainboard/google/jecht/devicetree.cb') diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 4d16ed694f..8a2129f4eb 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -9,9 +9,6 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - - - register "pirqa_routing" = "0x8b" register "pirqb_routing" = "0x8a" register "pirqc_routing" = "0x8b" @@ -84,8 +81,14 @@ chip soc/intel/broadwell register "skip_keyboard" = "1" # Enable PECI on TMPIN3 register "peci_tmpin" = "3" + # Disable use of TMPIN1 + register "tmpin1_mode" = "0" + # Enable Thermal Diode on TMPIN2 + register "tmpin2_mode" = "1" # Enable FAN2 register "fan2_enable" = "1" + # Default FAN2 speed + register "fan2_speed" = "0x4d" device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 -- cgit v1.2.3