From 6f174ee0dda132d1d8e18398a79ecba99094a068 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Fri, 23 Jun 2017 13:07:10 -0600 Subject: google/kahlee: Update for single DIMM Update for a single DIMM with an SPD at address A0. Change-Id: I646f079c99cbaffd7094773243600c3030308325 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/19833 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/mainboard/google/kahlee/OemCustomize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/kahlee/OemCustomize.c') diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 3893e5dbcb..2b3ac292f6 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -20,7 +20,7 @@ static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), MOTHER_BOARD_LAYERS(LAYERS_6), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, -- cgit v1.2.3