From b6ac3a299769ad458dbc28c6348f186342d4d556 Mon Sep 17 00:00:00 2001
From: Marc Jones <marcj303@gmail.com>
Date: Thu, 5 Oct 2017 21:57:33 -0600
Subject: kahlee: Set Kahlee GPEs

Add GPE configuration table.

Remove GPE3 from the power button ASL and set the EC to GPE3(AGPIO22).

Set the EC and PCIE/WLAN SCI GPIO signals.

Set GPE ASL methods for:
  PCIE/WLAN      8h
  EHCI          18h
  XHCI          1fh
Note EC GPE3 methods are in the EC ASL.

BUG=b:63268311
BRANCH=none
TEST=Test lidswitch powers the device on and off at the login screen.

Change-Id: I27c880ee84b6797d999d4d5951602b654ede948e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22096
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/kahlee/mainboard.c | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src/mainboard/google/kahlee/mainboard.c')

diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index 48a05a97d7..c7689c892d 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -19,6 +19,8 @@
 #include <agesawrapper.h>
 #include <amd_pci_util.h>
 #include <ec.h>
+#include <mainboard.h>
+#include <soc/smi.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 /***********************************************************
@@ -79,7 +81,13 @@ static void pirq_setup(void)
 
 static void mainboard_init(void *chip_info)
 {
+	const struct sci_source *gpes;
+	size_t num;
+
 	mainboard_ec_init();
+
+	gpes = get_gpe_table(&num);
+	gpe_configure_sci(gpes, num);
 }
 
 /*************************************************
-- 
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