From 5b044ae6077bfd6bbc162741cc5b3086dbf56d34 Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Sat, 25 Oct 2014 15:20:55 +0200 Subject: bd82x6x: Move to common FADT. Change-Id: I04ed600796c55f5af4f0a07687f676e6484a9830 Signed-off-by: Vladimir Serbinenko Reviewed-on: http://review.coreboot.org/7200 Reviewed-by: Nicolas Reinecke Reviewed-by: Edward O'Callaghan Tested-by: build bot (Jenkins) --- src/mainboard/google/link/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/google/link/devicetree.cb') diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 8f0ed3c7e8..15aa432e64 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -72,6 +72,9 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "1" + register "p_cnt_throttling_supported" = "0" + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R -- cgit v1.2.3