From 49428d840323210433c96740545246296d65b3f2 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Thu, 21 Feb 2013 15:48:37 -0800 Subject: Add support for Google's Chromebook Pixel Ladies and gentlemen, I'm very happy to announce coreboot support for the latest and greatest Google Chromebook: The Chromebook Pixel. See the link below for more information on the Chromebook Pixel, and its exciting specs: http://www.google.com/intl/en/chrome/devices/chromebooks.html#pixel The device is running coreboot and open source firmware on the EC (see ChromeEC commit for more information on that exciting topic) Change-Id: I03d00cf391bbb1a32f330793fe9058493e088571 Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/2482 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/mainboard/google/link/i915io.c | 755 +++++++++++++++++++++++++++++++++++++ 1 file changed, 755 insertions(+) create mode 100644 src/mainboard/google/link/i915io.c (limited to 'src/mainboard/google/link/i915io.c') diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c new file mode 100644 index 0000000000..98c73b7193 --- /dev/null +++ b/src/mainboard/google/link/i915io.c @@ -0,0 +1,755 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "i915io.h" + +struct iodef iodefs[] = { +{V,0,}, +//{V, 7, }, +{W, 1, "", PCH_GMBUS0, 0x00000000, }, +{R, 1, "", PP_ON_DELAYS, 0x00000000, }, +{R, 1, "", PP_OFF_DELAYS, 0x00000000, }, +{W, 1, "", PP_ON_DELAYS, 0x019007d0, }, +{W, 1, "", PP_OFF_DELAYS, 0x015e07d0, }, +{M, 1, "[drm:intel_detect_pch], Found PatherPoint PCH"}, +{M, 1, "[drm:i915_load_modeset_init], failed to find VBIOS tables"}, +{R, 50, "", 0x130040, 0x00000001, 10}, +{W, 1, "", 0xa188, 0x00010001, }, +{R, 1, "", 0xa188, 0x00010001, }, +{R, 1, "", 0x130040, 0x00000001, }, +{R, 1, "", 0x13805c, 0x40000000, }, +{R, 1, "", 0xa180, 0x84100020, }, +{W, 1, "", 0xa188, 0x00010000, }, +{R, 1, "", 0x120000, 0x00000000, }, +{M, 1, "[drm:intel_init_display], Using MT version of forcewake"}, +{R, 1, "", 0x145d10, 0x2010040c, }, +{M, 1, "[drm:intel_modeset_init], 3 display pipes available."}, +{R, 1, "", _PIPEACONF, 0x00000000, }, +{W, 1, "", _PIPEACONF, 0x00000000, }, +{R, 1, "", _PIPEBCONF, 0x00000000, }, +{W, 1, "", _PIPEBCONF, 0x00000000, }, +{R, 1, "", 0x72008, 0x00000000, }, +{W, 1, "", 0x72008, 0x00000000, }, +{R, 1, "", _PIPEACONF, 0x00000000, }, +{W, 1, "", _PIPEACONF, 0x00000000, }, +{R, 1, "", _PIPEBCONF, 0x00000000, }, +{W, 1, "", _PIPEBCONF, 0x00000000, }, +{R, 1, "", 0x72008, 0x00000000, }, +{W, 1, "", 0x72008, 0x00000000, }, +{R, 1, "", _PIPEACONF, 0x00000000, }, +{W, 1, "", _PIPEACONF, 0x00000000, }, +{R, 1, "", _PIPEBCONF, 0x00000000, }, +{W, 1, "", _PIPEBCONF, 0x00000000, }, +{R, 1, "", 0x72008, 0x00000000, }, +{W, 1, "", 0x72008, 0x00000000, 300}, +{W, 1, "", CPU_VGACNTRL, 0x80000000, }, +{R, 1, "", CPU_VGACNTRL, 0x80000000, }, +{R, 1, "", 0x64000, 0x0000001c, }, +{R, 1, "", PCH_PP_ON_DELAYS, 0x47d007d0, }, +{R, 1, "", PCH_PP_OFF_DELAYS, 0x01f407d0, }, +{R, 1, "", PCH_PP_DIVISOR, 0x00186906, }, +{M, 1, "[drm:intel_dp_init], cur t1_t3 2000 t8 2000 t9 2000 t10 500" + "t11_t12 6000"}, +{M, 1, "[drm:intel_dp_init], vbt t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0"}, +{M, 1, "[drm:intel_dp_init], panel power up delay 200," + "power down delay 50, power cycle delay 600"}, +{M, 1, "[drm:intel_dp_init], backlight on delay 200, off delay 200"}, +{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on"}, +{R, 1, "", PCH_PP_CONTROL, 0x00000000, }, +{R, 1, "", PCH_PP_STATUS, 0x00000000, }, +{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle"}, +{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:00000000"}, +{R, 2, "", PCH_PP_STATUS, 0x00000000, }, +{R, 1, "", PCH_PP_CONTROL, 0x00000000, }, +{W, 1, "", PCH_PP_CONTROL, 0xabcd0008, }, +{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, }, +{M, 1, "[drm:ironlake_edp_panel_vdd_on], R PCH_PP_CONTROL:abcd0008"}, +{R, 2, "", PCH_PP_STATUS, 0x00000000, }, +{M, 1, "[drm:ironlake_edp_panel_vdd_on], eDP was not running"}, +{R, 1, "", PCH_PP_STATUS, 0x00000000, }, +{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, }, +{R, 1, "", PCH_PP_STATUS, 0x00000000, }, +{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, }, +{R, 1, "", DPA_AUX_CH_CTL, 0x014300c8, }, +{W, 1, "", DPA_AUX_CH_DATA1, 0x9000000e, }, +{W, 1, "", DPA_AUX_CH_CTL, 0xd24500c8, }, +{R, 2, "", DPA_AUX_CH_CTL, 0x814500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x807500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x810500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x410500c8, }, +{W, 1, "", DPA_AUX_CH_CTL, 0x530500c8, }, +{R, 1, "", DPA_AUX_CH_DATA1, 0x00110a84, }, +{R, 1, "", DPA_AUX_CH_DATA2, 0x41000001, }, +{R, 1, "", DPA_AUX_CH_DATA3, 0xc0020000, }, +{R, 1, "", DPA_AUX_CH_DATA4, 0x001f0000, }, +{M, 1, "[drm:intel_dp_i2c_init], i2c_init DPDDC-A"}, +{R, 1, "", PCH_PP_STATUS, 0x00000000, }, +{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, }, +{R, 1, "", PCH_PP_STATUS, 0x00000000, }, +{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, }, +{R, 1, "", DPA_AUX_CH_CTL, 0x010500c8, }, +{W, 1, "", DPA_AUX_CH_DATA1, 0x40000000, }, +{W, 1, "", DPA_AUX_CH_CTL, 0xd23500c8, }, +{R, 2, "", DPA_AUX_CH_CTL, 0x810500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, }, +{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, }, +{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, }, +{R, 1, "", PCH_PP_STATUS, 0x00000000, }, +{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, }, +{R, 1, "", PCH_PP_STATUS, 0x00000000, }, +{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, }, +{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, }, +{W, 1, "", DPA_AUX_CH_DATA1, 0x00000000, }, +{W, 1, "", DPA_AUX_CH_CTL, 0xd23500c8, }, +{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, }, +{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, }, +{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, }, +{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1"}, +{R, 1, "", BLC_PWM_CPU_CTL, 0x000010ce, }, +{M, 1, "[drm:intel_panel_get_backlight], get backlight PWM = 4302"}, +{M, 1, "[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f"}, +{M, 1, "[drm:intel_dp_i2c_aux_ch], aux_ch failed -110"}, +{M, 1, +"[drm:ironlake_init_pch_refclk], has_panel 1 has_lvds 0 has_pch_edp 0" + "has_cpu_edp 1 has_ck505 0"}, +{R, 1, "", PCH_DREF_CONTROL, 0x00000000, }, +{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on panel"}, +{W, 1, "", PCH_DREF_CONTROL, 0x00001402, }, +{R, 1, "", PCH_DREF_CONTROL, 0x00001402, 200}, +{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on eDP"}, +{W, 1, "", PCH_DREF_CONTROL, 0x00005402, }, +{R, 1, "", PCH_DREF_CONTROL, 0x00005402, 200}, +{W, 1, "", ILK_DSPCLK_GATE, 0x10000000, }, +{W, 1, "", WM3_LP_ILK, 0x00000000, }, +{W, 1, "", WM2_LP_ILK, 0x00000000, }, +{W, 1, "", WM1_LP_ILK, 0x00000000, }, +{W, 1, "", 0x9404, 0x00002000, }, +{W, 1, "", ILK_DSPCLK_GATE, 0x10000000, }, +{W, 1, "", IVB_CHICKEN3, 0x00000024, }, +{W, 1, "", 0x7010, 0x04000400, }, +{W, 1, "", 0xb01c, 0x3c4fff8c, }, +{W, 1, "", 0xb030, 0x20000000, }, +{R, 1, "", 0x9030, 0x00000000, }, +{W, 1, "", 0x9030, 0x00000800, }, +{R, 1, "", _DSPACNTR, 0x00000000, }, +{W, 1, "", _DSPACNTR, 0x00004000, }, +{R, 1, "", _DSPAADDR, 0x00000000, }, +{W, 1, "", _DSPAADDR, 0x00000000, }, +{R, 1, "", _DSPASIZE+0xc, 0x00000000, }, +{W, 1, "", _DSPASIZE+0xc, 0x00000000, }, +{R, 1, "", _DSPBCNTR, 0x00000000, }, +{W, 1, "", _DSPBCNTR, 0x00004000, }, +{R, 1, "", _DSPBADDR, 0x00000000, }, +{W, 1, "", _DSPBADDR, 0x00000000, }, +{R, 1, "", _DSPBSURF, 0x00000000, }, +{W, 1, "", _DSPBSURF, 0x00000000, }, +{R, 1, "", _DVSACNTR, 0x00000000, }, +{W, 1, "", _DVSACNTR, 0x00004000, }, +{R, 1, "", _DVSALINOFF, 0x00000000, }, +{W, 1, "", _DVSALINOFF, 0x00000000, }, +{R, 1, "", _DVSASURF, 0x00000000, }, +{W, 1, "", _DVSASURF, 0x00000000, }, +{W, 1, "", SOUTH_DSPCLK_GATE_D, 0x20000000, }, +{R, 1, "", SOUTH_CHICKEN2, 0x00000000, }, +{W, 1, "", SOUTH_CHICKEN2, 0x00000001, }, +{W, 1, "", _TRANSA_CHICKEN2, 0x80000000, }, +{W, 1, "", _TRANSB_CHICKEN2, 0x80000000, }, +/* to here, it works ok with v0 */ +//{V, 7,}, +{M, 1, "[drm:drm_edid_to_eld], ELD:no CEA Extension found"}, +{M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]" + "probed modes :"}, +{M, 1, "[drm:drm_mode_debug_printmodeline]," +"Modeline 0:\"2560x1700\" 60 285250 2560 2608 2640 2720 1700 1703 1713 1749" +"0x48 0xa"}, +{M, 1, "[drm:drm_setup_crtcs], "}, +{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes"}, +{M, 1, "[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config"}, +{M, 1, "[drm:drm_setup_crtcs], desired mode 2560x1700 set on crtc 3"}, +{M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]"}, +{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0"}, +{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on"}, +//{V, 7,}, +{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0"}, +{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes"}, +{M, 1, "[drm:intel_get_load_detect_pipe], [CONNECTOR:6:eDP-1]," +"[ENCODER:7:TMDS-7]"}, +{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4" +"clock 270000"}, +{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]"}, +{R, 1, "", PCH_PP_STATUS, 0x00000000, }, +{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, }, +{R, 1, "", PCH_PP_STATUS, 0x00000000, }, +{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, }, +{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, }, +{W, 1, "", DPA_AUX_CH_DATA1, 0x80060000, }, +{W, 1, "", DPA_AUX_CH_DATA2, 0x01000000, }, +{W, 1, "", DPA_AUX_CH_CTL, 0xd25500c8, }, +{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, }, +{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, }, +{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, }, +{R, 1, "", 0x64000, 0x0000001c, }, +{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1"}, +#if 0 +/* I hope we never try to use this. It is left here as a documentation thing. */ +/* SCALING HACK */ +/* these were determined by reading registers. + * They should stretch the display. + * They don't. + * From u-boot? After vbios? + */ +{V, 7, }, +{M, 1, "Turning on panel fitter (must be done before power cycle)"}, +{W, 1, "Enabled,PIPEA,Hardcoded edge enhance", _PFA_CTL_1, 0x80800000, }, +/* status: can't ever set vscale. + * Which may be why we get no display at all if we try. */ +{W, 1, "stretch", _PFA_VSCALE, /*0x00004000*/0xffffffff, }, +{W, 1, "stretch", _PFA_HSCALE, /*0x00004000*/0xffffffff, }, +{W, 1, "2560x1700", _PFA_WIN_SZ, 0x0a0006a4, }, +//{W, 1, "2560x1700", _PFA_WIN_SZ, 0x05000352, }, +{W, 1, "@[0,0]", _PFA_WIN_POS, 0x00000000, }, +{R, 1, "Vstretch", _PFA_VSCALE, 0x00004000, }, +{R, 1, "Hstretch", _PFA_HSCALE, 0x00004000, }, +{R, 1, "2560x1700", _PFA_WIN_SZ, 0x0a0006a4, }, +{R, 1, "@[0,0]", _PFA_WIN_POS, 0x00000000, }, +{R, 1, "Enabled,PIPEA,Hardcoded edge enhance", _PFA_CTL_1, 0x80800000, }, +{V,0,}, +/* END SCALING HACK */ +#endif +{R, 2, "", PCH_DP_D, 0x00000004, }, +{R, 1, "", _PIPEACONF, 0x00000000, }, +{W, 1, "", _PIPEACONF, 0x00000040, }, +{R, 1, "", _PIPEACONF, 0x00000040, }, +{M, 1, "[drm:ironlake_crtc_mode_set], Mode for pipe 0:"}, +{M, 1, "[drm:drm_mode_debug_printmodeline]," +"Modeline 0:\"2560x1700\" 60 285250 2560 2608 2640 2720 1700 1703 1713 1749" +" 0x48 0xa"}, +{W, 1, "", _TRANSA_DATA_M1, 0x00000000, }, +{W, 1, "", _TRANSA_DATA_N1, 0x00000000, }, +{W, 1, "", _TRANSA_DP_LINK_M1, 0x00000000, }, +{W, 1, "", _TRANSA_DP_LINK_N1, 0x00000000, }, +{W, 1, "", _PCH_FPA1, 0x00020e08, }, +{W, 1, "", _VSYNCSHIFT_A, 0x00000000, }, +{W, 1, "", _HTOTAL_A, 0x0a9f09ff, }, +{W, 1, "", _HBLANK_A, 0x0a9f09ff, }, +{W, 1, "", _HSYNC_A, 0x0a4f0a2f, }, +{W, 1, "", _VTOTAL_A, 0x06d406a3, }, +{W, 1, "", _VBLANK_A, 0x06d406a3, }, +{W, 1, "", _VSYNC_A, 0x06b006a6, }, +{W, 1, "", _PIPEASRC, 0x09ff06a3, }, +{W, 1, "", _PIPEA_DATA_M1, 0x7e4e58a4, }, +{W, 1, "", _PIPEA_DATA_N1, 0x0083d600, }, +{W, 1, "", _PIPEA_LINK_M1, 0x00045a42, }, +{W, 1, "", _PIPEA_LINK_N1, 0x00041eb0, }, +{M, 1, "[drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000"}, +{R, 1, "", 0x64000, 0x0000001c, }, +{W, 1, "", 0x64000, 0x0000001c, }, +{R, 1, "", 0x64000, 0x0000001c, 500}, +{W, 1, "", _PIPEACONF, 0x00000050, }, +{R, 1, "", _PIPEACONF, 0x00000050, }, +{R, 1, "", _PIPEASTAT, 0x00000000, }, +{W, 1, "", _PIPEASTAT, 0x00000002, }, +{R, 4562, "", _PIPEASTAT, 0x00000000, }, +{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out"}, +{W, 1, "", _DSPACNTR, 0x40000000, }, +{R, 2, "", _DSPACNTR, 0x40000000, }, +{W, 1, "", _DSPACNTR, 0x58004000, }, +{M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240"}, +{W, 1, "", _DSPASTRIDE, 0x00002800, }, +{W, 1, "", _DSPASIZE+0xc, 0x00000000, }, +{W, 1, "", _DSPACNTR+0x24, 0x00000000, }, +{W, 1, "", _DSPAADDR, 0x00000000, }, +{R, 1, "", _DSPACNTR, 0x58004000, }, +{R, 1, "", 0x145d10, 0x2010040c, }, +{R, 1, "", WM0_PIPEA_ILK, 0x00783818, }, +{W, 1, "", WM0_PIPEA_ILK, 0x00183806, }, +{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24," +"cursor:6"}, +{W, 1, "", WM3_LP_ILK, 0x00000000, }, +{W, 1, "", WM2_LP_ILK, 0x00000000, }, +{W, 1, "", WM1_LP_ILK, 0x00000000, }, +{R, 1, "", 0x145d10, 0x2010040c, }, +{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3," +"cursor 6"}, +{R, 1, "", 0x145d10, 0x2010040c, }, +{W, 1, "", WM1_LP_ILK, 0x84302606, }, +{R, 1, "", 0x145d10, 0x2010040c, }, +{M, 1,"[drm:ironlake_check_srwm], watermark 2:display plane 145, fbc lines 3," + "cursor 6"}, +{R, 1, "", 0x145d10, 0x2010040c, }, +{W, 1, "", WM2_LP_ILK, 0x90309106, }, +{R, 1, "", 0x145d10, 0x2010040c, }, +{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, fbc lines 4," + "cursor 10"}, +{R, 1, "", 0x145d10, 0x2010040c, }, +{W, 1, "", WM3_LP_ILK, 0xa041200a, }, +{M, 1, "[drm:drm_crtc_helper_set_mode], [ENCODER:7:TMDS-7]" + "set [MODE:0:2560x1700]"}, +{M, 1, "[drm:ironlake_edp_pll_on], "}, +{R, 1, "", 0x64000, 0x0000001c, }, +{W, 1, "", 0x64000, 0x0000401c, }, +{R, 1, "", 0x64000, 0x0000401c, 200}, +{R, 1, "", 0x64000, 0x0000401c, }, +{R, 1, "", 0x145d10, 0x2010040c, }, +{R, 1, "", WM0_PIPEA_ILK, 0x00183806, }, +{W, 1, "", WM0_PIPEA_ILK, 0x00183806, }, +{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24," +"cursor:6"}, +{W, 1, "", WM3_LP_ILK, 0x00000000, }, +{W, 1, "", WM2_LP_ILK, 0x00000000, }, +{W, 1, "", WM1_LP_ILK, 0x00000000, }, +{R, 1, "", 0x145d10, 0x2010040c, }, +{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3," + "cursor 6"}, +{R, 1, "", 0x145d10, 0x2010040c, }, +{W, 1, "", WM1_LP_ILK, 0x84302606, }, +{R, 1, "", 0x145d10, 0x2010040c, }, +{M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, fbc lines 3," + "cursor 6"}, +{R, 1, "", 0x145d10, 0x2010040c, }, +{W, 1, "", WM2_LP_ILK, 0x90309106, }, +{R, 1, "", 0x145d10, 0x2010040c, }, +{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, fbc lines 4," + "cursor 10"}, +{R, 1, "", 0x145d10, 0x2010040c, }, +{W, 1, "", WM3_LP_ILK, 0xa041200a, }, +{R, 1, "", _FDI_TXA_CTL, 0x00040000, }, +{W, 1, "", _FDI_TXA_CTL, 0x00040000, }, +{R, 1, "", _FDI_TXA_CTL, 0x00040000, }, +{R, 1, "", _FDI_RXA_CTL, 0x00000040, }, +{R, 1, "", _PIPEACONF, 0x00000050, }, +{W, 1, "", _FDI_RXA_CTL, 0x00020040, }, +{R, 1, "", _FDI_RXA_CTL, 0x00020040, 100}, +{R, 1, "", SOUTH_CHICKEN1, 0x00000000, }, +{W, 2, "", SOUTH_CHICKEN1, 0x00000000, }, +{R, 1, "", SOUTH_CHICKEN1, 0x00000000, }, +{R, 1, "", _FDI_TXA_CTL, 0x00040000, }, +{W, 1, "", _FDI_TXA_CTL, 0x00040000, }, +{R, 1, "", _FDI_RXA_CTL, 0x00020040, }, +{R, 1, "", _PIPEACONF, 0x00000050, }, +{W, 1, "", _FDI_RXA_CTL, 0x00020040, }, +{R, 1, "", _FDI_RXA_CTL, 0x00020040, 100}, +{W, 1, "", _LGC_PALETTE_A, 0x00000000, }, +{W, 1, "", _LGC_PALETTE_A+0x4, 0x00010101, }, +{W, 1, "", _LGC_PALETTE_A+0x8, 0x00020202, }, +{W, 1, "", _LGC_PALETTE_A+0xc, 0x00030303, }, +{W, 1, "", _LGC_PALETTE_A+0x10, 0x00040404, }, +{W, 1, "", _LGC_PALETTE_A+0x14, 0x00050505, }, +{W, 1, "", _LGC_PALETTE_A+0x18, 0x00060606, }, +{W, 1, "", _LGC_PALETTE_A+0x1c, 0x00070707, }, +{W, 1, "", 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1, "", 0x4a3e8, 0x00fafafa, }, +{W, 1, "", 0x4a3ec, 0x00fbfbfb, }, +{W, 1, "", 0x4a3f0, 0x00fcfcfc, }, +{W, 1, "", 0x4a3f4, 0x00fdfdfd, }, +{W, 1, "", 0x4a3f8, 0x00fefefe, }, +{W, 1, "", 0x4a3fc, 0x00ffffff, }, +{R, 1, "", _PIPEACONF, 0x00000050, }, +{W, 1, "", _PIPEACONF, 0x80000050, }, +{R, 1, "", _PIPEASTAT, 0x00000000, }, +{W, 1, "", _PIPEASTAT, 0x00000002, }, +{R, 4533, "", _PIPEASTAT, 0x00000000, }, +{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out"}, +{R, 1, "", _PIPEACONF, 0xc0000050, }, +{R, 1, "", _DSPACNTR, 0x58004000, }, +{W, 1, "", _DSPACNTR, 0xd8004000, }, +{R, 1, "", _DSPAADDR, 0x00000000, }, +{W, 1, "", _DSPAADDR, 0x00000000, }, +{R, 1, "", _DSPASIZE+0xc, 0x00000000, }, +{W, 1, "", _DSPASIZE+0xc, 0x00000000, }, +{R, 1, "", _PIPEASTAT, 0x00000000, }, +{W, 1, "", _PIPEASTAT, 0x00000002, }, +{R, 4392, "", _PIPEASTAT, 0x00000000, }, +{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out"}, +{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on"}, +{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, }, +{M, 1, "[drm:ironlake_edp_panel_on], Turn eDP power on"}, +{R, 1, "", PCH_PP_STATUS, 0x00000000, }, +{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle"}, +{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd0008"}, +{R, 2, "", PCH_PP_STATUS, 0x00000000, }, +{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, }, +{W, 1, "", PCH_PP_CONTROL, 0xabcd000b, }, +{R, 1, "", PCH_PP_CONTROL, 0xabcd000b, }, +{M, 1, "[drm:ironlake_wait_panel_on], Wait for panel power on"}, +{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd000b"}, +{R, 4, "", PCH_PP_STATUS, 0x0000000a, }, +{R, 16983, "", PCH_PP_STATUS, 0x9000000a, }, +{R, 17839, "", PCH_PP_STATUS, 0x90000009, }, +{R, 1, "", PCH_PP_STATUS, 0x80000008, }, +//{V, 7,}, +{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1"}, +{R, 2, "", PCH_PP_CONTROL, 0xabcd000b, }, +{W, 1, "", PCH_PP_CONTROL, 0xabcd0003, }, +{R, 1, "", PCH_PP_CONTROL, 0xabcd0003, }, +{M, 1, "[drm:ironlake_panel_vdd_off_sync], R PCH_PP_CONTROL:abcd0003"}, +{R, 1, "", PCH_PP_STATUS, 0x80000008, }, +{W, 1, "", 0x64000, 0x8e1c4104, }, +{R, 1, "", 0x64000, 0x8e1c4104, }, +{R, 2, "", PCH_PP_STATUS, 0x80000008, }, +{R, 1, "", 0x64000, 0x8cdc4104, }, +{M, 1, "[drm:intel_dp_link_down], "}, +{W, 1, "", 0x64000, 0x8e1c0004, }, +{R, 1, "", 0x64000, 0x8e1c0004, 100}, +{W, 1, "", 0x64000, 0x8e1c0204, }, +{R, 1, "", 0x64000, 0x8e1c0204, }, +{W, 1, "", 0x64000, 0x0e1c0304, }, +{R, 2, "", 0x64000, 0x0e1c0304, }, +{R, 2, "", PCH_PP_STATUS, 0x80000008, }, +{R, 1, "", DPA_AUX_CH_CTL, 0x007500c8, }, +{W, 1, "", DPA_AUX_CH_DATA1, 0x80010008, }, +{W, 1, "", DPA_AUX_CH_DATA2, 0x0a840000, }, +{W, 1, "", DPA_AUX_CH_DATA3, 0x00000000, }, +{W, 1, "", DPA_AUX_CH_DATA4, 0x01000000, }, +{W, 1, "", DPA_AUX_CH_CTL, 0xd2d500c8, }, +{R, 3, "", DPA_AUX_CH_CTL, 0x807500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, }, +{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, }, +{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, }, +{W, 1, "", 0x64000, 0x891c4004, }, +{R, 1, "", 0x64000, 0x891c4004, }, +{R, 2, "", PCH_PP_STATUS, 0x80000008, }, +{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, }, +{W, 1, "", DPA_AUX_CH_DATA1, 0x80010200, }, +{W, 1, "", DPA_AUX_CH_DATA2, 0x21000000, }, +{W, 1, "", DPA_AUX_CH_CTL, 0xd25500c8, }, +{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, }, +{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, }, +{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, }, +{R, 2, "", PCH_PP_STATUS, 0x80000008, }, +{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, }, +{W, 1, "", DPA_AUX_CH_DATA1, 0x80010303, }, +{W, 1, "", DPA_AUX_CH_DATA2, 0x00000000, }, +{W, 1, "", DPA_AUX_CH_CTL, 0xd28500c8, }, +{R, 3, "", DPA_AUX_CH_CTL, 0x801500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, }, +{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, }, +{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, 100}, +{R, 2, "", PCH_PP_STATUS, 0x80000008, }, +{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, }, +{W, 1, "", DPA_AUX_CH_DATA1, 0x90020205, }, +{W, 1, "", DPA_AUX_CH_CTL, 0xd24500c8, }, +{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x804500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x407500c8, }, +{W, 1, "", DPA_AUX_CH_CTL, 0x527500c8, }, +{R, 1, "", DPA_AUX_CH_DATA1, 0x00111180, }, +{R, 1, "", DPA_AUX_CH_DATA2, 0x02000000, }, +{M, 1, "[drm:intel_dp_start_link_train], clock recovery OK"}, +{W, 1, "", 0x64000, 0x891c4104, }, +{R, 1, "", 0x64000, 0x891c4104, }, +{R, 2, "", PCH_PP_STATUS, 0x80000008, }, +{R, 1, "", DPA_AUX_CH_CTL, 0x007500c8, }, +{W, 1, "", DPA_AUX_CH_DATA1, 0x80010200, }, +{W, 1, "", DPA_AUX_CH_DATA2, 0x22000000, }, +{W, 1, "", DPA_AUX_CH_CTL, 0xd25500c8, }, +{R, 2, "", DPA_AUX_CH_CTL, 0x807500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, }, +{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, }, +{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, }, +{R, 2, "", PCH_PP_STATUS, 0x80000008, }, +{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, }, +{W, 1, "", DPA_AUX_CH_DATA1, 0x80010303, }, +{W, 1, "", DPA_AUX_CH_DATA2, 0x00000000, }, +{W, 1, "", DPA_AUX_CH_CTL, 0xd28500c8, }, +{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x800500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, }, +{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, }, +{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, 400}, +{R, 2, "", PCH_PP_STATUS, 0x80000008, }, +{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, }, +{W, 1, "", DPA_AUX_CH_DATA1, 0x90020205, }, +{W, 1, "", DPA_AUX_CH_CTL, 0xd24500c8, }, +{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x804500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x407500c8, }, +{W, 1, "", DPA_AUX_CH_CTL, 0x527500c8, }, +{R, 1, "", DPA_AUX_CH_DATA1, 0x00777781, }, +{R, 1, "", DPA_AUX_CH_DATA2, 0x02000000, }, +{W, 1, "", 0x64000, 0x891c4304, }, +{R, 1, "", 0x64000, 0x891c4304, }, +{R, 2, "", PCH_PP_STATUS, 0x80000008, }, +{R, 1, "", DPA_AUX_CH_CTL, 0x007500c8, }, +{W, 1, "", DPA_AUX_CH_DATA1, 0x80010200, }, +{W, 1, "", DPA_AUX_CH_DATA2, 0x00000000, }, +{W, 1, "", DPA_AUX_CH_CTL, 0xd25500c8, }, +{R, 2, "", DPA_AUX_CH_CTL, 0x807500c8, 100}, +{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, }, +{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, }, +{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, }, +{M, 1, "[drm:ironlake_edp_backlight_on], "}, +{R, 1, "", PCH_PP_CONTROL, 0xabcd0003, }, +{W, 1, "", PCH_PP_CONTROL, 0xabcd0007, }, +{R, 1, "", PCH_PP_CONTROL, 0xabcd0007, }, +{R, 1, "", _PIPEADSL, 0x00000633, 500}, +{R, 1, "", _PIPEADSL, 0x00000652, }, +{R, 1, "", _PIPEASTAT, 0x00000000, }, +{W, 1, "", _PIPEASTAT, 0x00000002, }, +{R, 5085, "", _PIPEASTAT, 0x00000000, }, +{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out"}, +{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4" + "clock 270000"}, +{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]"}, +{0,}, +}; -- cgit v1.2.3