From 64925b5128d8ed27bd1780f6cb25805aecc659e6 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Fri, 11 Jan 2019 07:54:48 -0800 Subject: soc/mainboard: Update mainboard UART Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After f5ca922 (Untangle CBFS microcode updates) got merged, all mainboard using intel apollolake, cannonlake, coffeelake, glk, kabylake, skylake, icelake and whiskeylake get affected. Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG and set default console for each platform. BUG=N/A TEST=Build and test on Sarien platform, by default we can still get console from cbmem, and enable CONSOLE_SERIAL can get logs from UART port 2. Signed-off-by: Lijian Zhao Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de Reviewed-on: https://review.coreboot.org/c/30853 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Bora Guvendik Reviewed-by: Kyösti Mälkki --- src/mainboard/google/octopus/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google/octopus/Kconfig') diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 15230dcae7..a237741195 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -13,6 +13,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select SOC_ESPI select MAINBOARD_HAS_SPI_TPM_CR50 -- cgit v1.2.3