From 635e512be3cc0d805c9eb924a08528a39c0d6b1e Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Thu, 14 Jun 2018 12:39:56 +0900 Subject: mb/google/poppy/variants/nautilus: Correct USB OC pin configuration Due to schematic, we need to correct USB OC pin configuration. - OC0 for Type-C Port 1 - OC1 for Type-C Port 0 - OC2 for Type-A Port - OC3 to NC BUG=NONE BRANCH=poppy TEST=emerge-nautilus coreboot Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687 Signed-off-by: Seunghwan Kim Reviewed-on: https://review.coreboot.org/27099 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/poppy/variants/nautilus/devicetree.cb | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/mainboard/google/poppy/variants/nautilus/devicetree.cb') diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 39d7353f58..79bb5fbe27 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -167,16 +167,16 @@ chip soc/intel/skylake # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port + register "usb2_ports[0]" = "USB2_PORT_LONG(OC1)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC2)" # Type-A Port register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 + register "usb2_ports[4]" = "USB2_PORT_LONG(OC0)" # Type-C Port 2 register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # H1 register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # Camera - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # Intel Common SoC Config -- cgit v1.2.3