From 97c5464443306f26b61cec3a0f50108a5c06b7ef Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Sun, 10 May 2020 01:24:11 +0530 Subject: skylake: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Skylake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on nami system Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/poppy/variants/soraka/devicetree.cb | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google/poppy/variants/soraka') diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 146d8d2c19..8c22adea2f 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -268,9 +268,11 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "psys_pmax" = "45" # PL2 override 15W for KBL-Y - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + .psys_pmax = 45, + }" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration -- cgit v1.2.3