From c0b9c8cbc014662dccdab98841a47dca2570dc0d Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Fri, 1 Nov 2019 12:16:03 +0200 Subject: mb/google/poppy: Rework OV5670 power on sequence MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In particular: - Enable regulators *after* configuring the voltage - Allow 1 ms for the voltages to settle - Enable clock after powering on regulators - Remove extra delays between enabling things. The sensor requires 8192 clock cycles after the reset is lifted before I²C access, so 1 ms is enough. - Make the delay after lifting xshutdown 10 ms. This guarantees that streaming will only start once the sensor has had enough time to settle after lifting the reset. BUG=chromium:959232 Signed-off-by: Sakari Ailus Tested-by: Jacopo Mondi Change-Id: I4589a7d7ec324f4520572a406cc11ad3feec8b21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36723 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Furquan Shaikh --- .../include/baseboard/acpi/camera_pmic.asl | 29 ++++++++++++++-------- 1 file changed, 19 insertions(+), 10 deletions(-) (limited to 'src/mainboard/google/poppy') diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 12c3c22e1b..355b25528e 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -526,30 +526,39 @@ Scope (\_SB.PCI0.I2C2) daisy chain */ DOVD(1) - VAX2 = 1 /* Enable VAUX2 */ - if (LNotEqual (AX2V, 52)) { /* Set VAUX2 as 1.8006 V */ AX2V = 52 } - Sleep(1) + VAX2 = 1 /* Enable VAUX2 */ - \_SB.PCI0.I2C2.PMIC.CLKE() - CLE1 = 1 + \_SB.PCI0.I2C2.PMIC.CGP4(1) + + /* + * Wait for DOVDD and AVDD + * to settle. + */ + Sleep(1) - VAX1 = 1 /* Enable VAUX1 */ if (LNotEqual (AX1V, 19)) { /* Set VAUX1 as 1.2132V */ AX1V = 19 } - Sleep(3) + VAX1 = 1 /* Enable VAUX1 */ - \_SB.PCI0.I2C2.PMIC.CGP4(1) - Sleep(3) + /* Wait for VDD to settle. */ + Sleep(1) + + \_SB.PCI0.I2C2.PMIC.CLKE() + CLE1 = 1 \_SB.PCI0.I2C2.PMIC.CGP5(1) - Sleep(3) + /* + * Ensure 10 ms between + * power-up and streamon. + */ + Sleep(10) STA = 1 } } -- cgit v1.2.3