From 2715cdb3f32fcebdd1de6870a665a2b613c07e60 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 30 Oct 2019 16:48:19 +0530 Subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to refer sleepstates.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS. Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/reef/dsdt.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/reef') diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index 2b2f522661..29b816586c 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -45,7 +45,7 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) -- cgit v1.2.3