From 1fb6c01688d2728317f6a533302e51ef6c9c5fd1 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 12 Aug 2014 17:20:42 -0700 Subject: rush: support for DMA region Currently rush needs a DMA region in order to communicate with USB devices. Therefore, add that region to the memory map. BUG=chrome-os-partner:31293 BRANCH=None TEST=With the changes for adding non-cacheable memory range and adding DMA region, booting from USB reaches same point as MMC. Change-Id: I82d97840fad8cc96bf958c6efa13d2fdc1233d79 Signed-off-by: Patrick Georgi Original-Commit-Id: b182651a1b6db1a7adbf315b6865467590a0785c Original-Change-Id: I6a465eaa77e0d5ab4d5fb22161e88e7a5fd9c4a8 Original-Signed-off-by: Furquan Shaikh Original-Reviewed-on: https://chromium-review.googlesource.com/212193 Original-Tested-by: Furquan Shaikh Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Furquan Shaikh Reviewed-on: http://review.coreboot.org/8928 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/rush/Kconfig | 8 ++++++++ src/mainboard/google/rush/mainboard.c | 21 +++++++++++++++++++++ 2 files changed, 29 insertions(+) (limited to 'src/mainboard/google/rush') diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig index eaae86ce8c..f723a6c10d 100644 --- a/src/mainboard/google/rush/Kconfig +++ b/src/mainboard/google/rush/Kconfig @@ -95,4 +95,12 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 1 +config DRAM_DMA_START + hex + default 0xc0000000 + +config DRAM_DMA_SIZE + hex + default 0x00200000 + endif # BOARD_GOOGLE_RUSH diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c index c4b0b441c4..35417f07ce 100644 --- a/src/mainboard/google/rush/mainboard.c +++ b/src/mainboard/google/rush/mainboard.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include +#include #include #include #include @@ -86,3 +88,22 @@ struct chip_operations mainboard_ops = { .name = "rush", .enable_dev = mainboard_enable, }; + + +void mainboard_add_memory_ranges(struct memranges *map) +{ + /* Create non-cacheable region for DMA operations. */ + memranges_insert(map, CONFIG_DRAM_DMA_START, CONFIG_DRAM_DMA_SIZE, + MA_MEM | MA_MEM_NC | MA_NS | MA_RW); +} + +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = CONFIG_DRAM_DMA_START; + dma->range_size = CONFIG_DRAM_DMA_SIZE; +} -- cgit v1.2.3