From ddc3e42c2267fe175dcc28e38f53f0adecf1aa4e Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 2 Oct 2013 16:10:54 -0700 Subject: samus: Add coreboot board Add the coreboot board files for samus - Based on Bolt - GPIO setup based on 0.91 schematic - Support both memory types - No HDA verb table for this platform - Some GPIO interrupts are shared and need to be passed to OS Change-Id: I8dbd7639456c631a0115b03a493d94b5e2361ab5 Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/171694 Reviewed-by: Aaron Durbin (cherry picked from commit 249a74c628264e3d4ce754803ede31238404b4d5) Signed-off-by: Isaac Christensen Reviewed-on: http://review.coreboot.org/6775 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Stefan Reinauer --- src/mainboard/google/samus/Makefile.inc | 52 +++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 src/mainboard/google/samus/Makefile.inc (limited to 'src/mainboard/google/samus/Makefile.inc') diff --git a/src/mainboard/google/samus/Makefile.inc b/src/mainboard/google/samus/Makefile.inc new file mode 100644 index 0000000000..47cf9d6fd2 --- /dev/null +++ b/src/mainboard/google/samus/Makefile.inc @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c + +romstage-y += chromeos.c +ramstage-y += chromeos.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +## DIMM SPD for on-board memory +SPD_BIN = $(obj)/spd.bin + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = empty # 0: { 0, 0, 0 } +SPD_SOURCES += empty # 1: { 0, 0, 1 } +SPD_SOURCES += empty # 2: { 0, 1, 0 } +SPD_SOURCES += samsung_4Gb # 3: { 0, 1, 1 } +SPD_SOURCES += micron_4Gb # 4: { 1, 0, 0 } +SPD_SOURCES += samsung_8Gb # 5: { 1, 0, 1 } +SPD_SOURCES += micron_8Gb # 6: { 1, 1, 0 } +SPD_SOURCES += empty # 7: { 1, 1, 1 } + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do echo -e -n "\\x$$c"; \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := 0xab -- cgit v1.2.3