From de666dc9b86452d5efbda70aa2364877d2fcd449 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 13 Jun 2019 10:46:54 -0700 Subject: mb/google/sarien: Disable unused GPIOs These 4 GPIOs are being disconnected in the next board so use the board ID to configure these pins as not connected to ensure they do not cause leakage. Also remove the ACPI _PTS S5 code that was configuring the GPIOs. This does mean they will cause small leakage in S5 on existing boards, but it will not affect the new boards. BUG=b:132393441 TEST=boot on sarien with fake board ID and ensure that coreboot configures these pads as expected. Change-Id: I6ac04b9a635829811a09aeab7cba3bb58cfcff47 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/33450 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Bora Guvendik --- .../sarien/variants/arcada/include/variant/acpi/mainboard.asl | 9 --------- 1 file changed, 9 deletions(-) (limited to 'src/mainboard/google/sarien/variants/arcada') diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl index 4b05ba8e90..41121d28fe 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -15,8 +15,6 @@ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 -#define SSD_EN GPP_H13 -#define SSD_RST GPP_H12 /* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -37,13 +35,6 @@ Method (MPTS, 1) /* Clear touch screen pd pin to avoid leakage */ \_SB.PCI0.CTXS (TS_PD) - - /* Clear SSD EN adn RST pin to avoid leakage */ - If (Arg0 == 5) { - \_SB.PCI0.CTXS (SSD_RST) - Sleep(1) - \_SB.PCI0.CTXS (SSD_EN) - } } /* Method called from _WAK prior to wakeup */ -- cgit v1.2.3