From 59de870aa3f2bb758e6bb1deecc49e484cd9834a Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Mon, 17 Dec 2018 10:03:05 -0800 Subject: mb/google/sarien: Set Vref Config to 2 Accoding to desciption in FSP header, Vref Configuration will be set to 2 if VREF_CA to CH_A and VREF_DQ_B to CH_B. BUG=N/A TEST=Build and boot up on Arcada platform. Signed-off-by: Lijian Zhao Change-Id: I02e16e141b81d766a6060ca08283f432abd96647 Reviewed-on: https://review.coreboot.org/c/30280 Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/mainboard/google/sarien/romstage.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/google/sarien') diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c index 7284d5552b..95af0bc18c 100644 --- a/src/mainboard/google/sarien/romstage.c +++ b/src/mainboard/google/sarien/romstage.c @@ -37,6 +37,9 @@ static const struct cnl_mb_cfg memcfg = { /* Disable Early Command Training */ .ect = 0, + + /* Base on board design */ + .vref_ca_config = 2, }; void mainboard_memory_init_params(FSPM_UPD *memupd) -- cgit v1.2.3