From dacd5b9a6ad7d4273af83d356dc869660a04662e Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Wed, 29 May 2019 23:25:03 +0530 Subject: mb/google/sarien/variants/arcada: Set PCH Thermal Trip point to 77 degree C PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Arcada. Change-Id: I1915b974b10638b0f6ab97c6fb9b7a58d2cabc59 Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/33130 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/google/sarien') diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 1799127b6c..ebcf140b4c 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -164,6 +164,9 @@ chip soc/intel/cannonlake register "tcc_offset" = "1" + # PCH Thermal Trip Temperature in deg C + register "common_soc_config.pch_thermal_trip" = "77" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { -- cgit v1.2.3