From 1ae305efe1a0823c270767ddf6cc02c41ce146f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 4 Sep 2013 13:05:01 +0300 Subject: CBMEM: Add cbmem_late_set_table() and drop references to high_tables_base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This helper function is for compatibility only for chipsets that do not implement get_top_of_ram() to support early CBMEM. Also remove references to globals high_tables_base and _size under arch/ and from two ARMv7 boards. Change-Id: I17eee30635a0368b2ada06e0698425c5ef0ecc53 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/3902 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Aaron Durbin --- src/mainboard/google/snow/mainboard.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'src/mainboard/google/snow') diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 5aedac9646..8805be5fb7 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -262,17 +262,22 @@ static void mainboard_init(device_t dev) // gpio_info(); } +static void setup_cbmem(void) +{ + u64 size = CONFIG_COREBOOT_TABLES_SIZE; + u64 base = CONFIG_SYS_SDRAM_BASE + + ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - + CONFIG_COREBOOT_TABLES_SIZE; + cbmem_late_set_table(base, size); + cbmem_init(base, size); +} + static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; /* set up coreboot tables */ - /* FIXME: this should happen somewhere else */ - high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; - high_tables_base = CONFIG_SYS_SDRAM_BASE + - ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - - CONFIG_COREBOOT_TABLES_SIZE; - cbmem_init(high_tables_base, high_tables_size); + setup_cbmem(); /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ -- cgit v1.2.3